Yang Zhang

According to our database, Yang Zhang authored at least 12 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.

Chengning Wang, Dan Feng, Wei Tong, Yu Hua, Jingning Liu, Bing Wu, Wei Zhao, Linghao Song, Yang Zhang, Jie Xu, Xueliang Wei, Yiran Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage.

Chengning Wang, Dan Feng, Wei Tong, Jingning Liu, Bing Wu, Wei Zhao, Yang Zhang, Yiran Chen

IEEE Trans. Computers, 2021

EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture.

Yang Zhang, Zhibin Yu, Liang Gu, Chengning Wang, Dan Feng

IEEE Access, 2021

2020

A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches.

Bing Wu, Dan Feng, Wei Tong, Jingning Liu, Chengning Wang, Wei Zhao, Yang Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

Cross-point Resistive Memory: Nonideal Properties and Solutions.

Chengning Wang, Dan Feng, Wei Tong, Jingning Liu, Zheng Li, Jiayi Chang, Yang Zhang, Bing Wu, Jie Xu, Wei Zhao, Yilin Li, Ruoxi Ren

ACM Trans. Design Autom. Electr. Syst., 2019

FvRS: Efficiently identifying performance-critical data for improving performance of big data processing.

Gaoxiang Xu, Zhipeng Tan, Dan Feng, Laurence T. Yang, Wei Zhou, Xinyan Zhang, Yang Zhang, Jie Xu

Future Gener. Comput. Syst., 2019

Tiered-ReRAM: A Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture.

Yang Zhang, Dan Feng, Wei Tong, Jingning Liu, Chengning Wang, Jie Xu

Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019

2018

CACF: A Novel Circuit Architecture Co-optimization Framework for Improving Performance, Reliability and Energy of ReRAM-based Main Memory System.

Yang Zhang, Dan Feng, Wei Tong, Yu Hua, Jingning Liu, Zhipeng Tan, Chengning Wang, Bing Wu, Zheng Li, Gaoxiang Xu

ACM Trans. Archit. Code Optim., 2018

Asymmetric-ReRAM: A Low Latency and High Reliability Crossbar Resistive Memory Architecture.

Yang Zhang, Dan Feng, Zhipeng Tan, Jingning Liu, Wei Tong, Chengning Wang

Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

Aliens: a novel hybrid architecture for resistive random-access memory.

Bing Wu, Dan Feng, Wei Tong, Jingning Liu, Shuai Li, Mingshun Yang, Chengning Wang, Yang Zhang

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory.

Chengning Wang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Yang Zhang

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability.

Yang Zhang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Caihua Fang

Proceedings of the 54th Annual Design Automation Conference, 2017