Linghao Song

Orcid: 0000-0002-7450-2842

According to our database1, Linghao Song authored at least 41 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
LevelST: Stream-based Accelerator for Sparse Triangular Solver.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search.
CoRR, 2023

TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs.
CoRR, 2023

ReFloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers.
Proceedings of the International Conference for High Performance Computing, 2023

Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators.
Proceedings of the IEEE International Conference on Acoustics, 2022

Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

RAISE: A Resistive Accelerator for Subject-Independent EEG Signal Classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Accelerator Architectures for Deep Learning and Graph Processing.
PhD thesis, 2020

Low-Cost Floating-Point Processing in ReRAM for Scientific Computing.
CoRR, 2020

GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Parallelism in Deep Learning Accelerators.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
ReBNN: in-situ acceleration of binarized neural networks in ReRAM using complementary resistive cell.
CCF Trans. High Perform. Comput., 2019

How to Obtain and Run Light and Efficient Deep Learning Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

Deep Learning for Vertex Reconstruction of Neutrino-nucleus Interaction Events with Combined Energy and Time Data.
Proceedings of the IEEE International Conference on Acoustics, 2019

HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Taming extreme heterogeneity via machine learning based design of autonomous manycore systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

DPATCH: An Adversarial Patch Attack on Object Detectors.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019

2018
DPatch: Attacking Object Detectors with Adversarial Patches.
CoRR, 2018

GraphR: Accelerating Graph Processing Using ReRAM.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

ReRAM-based accelerator for deep learning.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReCom: An efficient resistive accelerator for compressed deep neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Atomlayer: a universal reRAM-based CNN accelerator with atomic layer computation.
Proceedings of the 55th Annual Design Automation Conference, 2018

ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
NVSim-VX<sup>s</sup>: an improved NVSim for variation aware STT-RAM simulation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A spiking neuromorphic design with resistive crossbar.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Spiking-based matrix computation by leveraging memristor crossbar array.
Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015


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