Yanquan Luo
Orcid: 0000-0003-1057-2996
According to our database1,
Yanquan Luo
authored at least 7 papers
between 2013 and 2025.
Collaborative distances:
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Bibliography
2025
A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
2018
IEEE J. Solid State Circuits, 2018
A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013