Yaseer Arafat Durrani

According to our database1, Yaseer Arafat Durrani authored at least 13 papers between 2006 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs.
J. Circuits Syst. Comput., 2018

2016
Efficient power analysis approach and its application to system-on-chip design.
Microprocess. Microsystems, 2016

2014
Power estimation for intellectual property-based digital systems at the architectural level.
J. King Saud Univ. Comput. Inf. Sci., 2014

High-Level Power Analysis for Intellectual Property-Based Digital Systems.
Circuits Syst. Signal Process., 2014

2011
Efficient power macromodeling technique for conventional MOS transistors.
Proceedings of the International Conference on Electrical Engineering and Informatics, 2011

2009
Power estimation technique for DSP architectures.
Digit. Signal Process., 2009

2007
Architectural Power Analysis for Intellectual Property-Based Digital System.
J. Low Power Electron., 2007

Efficient Power Macromodeling Technique for IP-Based Digital System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

LUT-Based Power Macromodeling Technique for DSP Architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Power Macromodeling for High Level Power Estimation.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Power Estimation for IP-Based Modules.
Proceedings of the International Symposium on System-on-Chip, 2006

Power estimation for register transfer level by genetic algorithm.
Proceedings of the ICINCO 2006, 2006

Power Macromodeling for IP Modules.
Proceedings of the 13th IEEE International Conference on Electronics, 2006


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