Yasmin Halawani

Orcid: 0000-0001-9617-5080

According to our database1, Yasmin Halawani authored at least 21 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
FORSA: Exploiting Filter Ordering to Reduce Switching Activity for Low Power CNNs.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Investigating the Connection Between Teachers' Factors and Students' Performance in Mathematics: A UAE Case Study.
Proceedings of the IEEE Frontiers in Education Conference, 2023

F-CNN: Faster CNN Exploiting Data Re-Use with Statistical Analysis.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Hyper-Dimensional Computing Challenges and Opportunities for AI Applications.
IEEE Access, 2022

2021
C3PU: Cross-Coupling Capacitor Processing Unit Using Analog-Mixed Signal In-Memory Computing for AI Inference.
CoRR, 2021

C3PU: Cross-Coupling Capacitor Processing Unit Using Analog-Mixed Signal for AI Inference.
IEEE Access, 2021

Design Exploration of ReRAM-Based Crossbar for AI Inference.
IEEE Access, 2021

SLID: Exploiting Spatial Locality in Input Data as a Computational Reuse Method for Efficient CNN.
IEEE Access, 2021

Fused RRAM-Based Shift-Add Architecture for Efficient Hyperdimensional Computing Paradigm.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020
FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks.
IEEE Access, 2020

Tunable Non-Volatile Analog Resistive Memory and Its Application in AI.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
ReRAM-Based In-Memory Computing for Search Engine and Neural Network Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

2018
Memristor-Based Hardware Accelerator for Image Compression.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Stateful Memristor-Based Search Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Re-configurable Memristor Array Structure for In-Memory Computing Applications.
Proceedings of the 30th International Conference on Microelectronics, 2018

2016
Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Memory impact on the lifetime of a Wireless Sensor Node using a Semi-Markov model.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
Memristor for energy efficient wireless sensor node.
Proceedings of the 8th International Design and Test Symposium, 2013

Embedded memory design using memristor: Retention time versus write energy.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Modeling of STT-MTJ for low power embedded memory applications: A comparative review.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Efficient power management in wireless sensor networks.
Proceedings of the 20th IEEE International Conference on Electronics, 2013


  Loading...