Yean-Yow Hwang

According to our database, Yean-Yow Hwang authored at least 9 papers between 1995 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Protecting Combinational Logic Synthesis Solutions.

Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2001

Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.

Jason Cong, Yean-Yow Hwang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.

Jason Cong, Yean-Yow Hwang

ACM Trans. Design Autom. Electr. Syst., 2000

1999

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections.

Jason Cong, Yean-Yow Hwang, Songjie Xu

Proceedings of the 36th Conference on Design Automation, 1999

1998

Intellectual property protection by watermarking combinational logic synthesis solutions.

Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.

Jason Cong, Yean-Yow Hwang

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997

Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping.

Jason Cong, Yean-Yow Hwang

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1996

Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design.

Jason Cong, Yean-Yow Hwang

Proceedings of the 33st Conference on Design Automation, 1996

1995

Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.

Jason Cong, Yean-Yow Hwang

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995