Yesong Jeong
According to our database1,
Yesong Jeong authored at least 2 papers
between 2024 and 2026.
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Bibliography
2026
A Fully Digital and Bias-Free Ternary Bus for Energy-Efficient On-Chip Interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2024
A 28-nm 323 TOPS/mm<sup>2</sup>/b and 2007 TOPS/W/b Ternary Latch Based Sparsity-Aware CIM Macro With Double-Sampling Ternary ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024