Yi-Hsiang Kao

Orcid: 0000-0002-6872-9979

According to our database1, Yi-Hsiang Kao authored at least 6 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
31.2 A Ripple-Less Buck Converter with Sub -21.94dB EVM for 5G Low Earth Orbit Application.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

8.11 A 48V-to-5V Buck Converter with Triple EMI Suppression Circuit Meeting CISPR 25 Automotive Standards.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
3D Wireless Power Transfer with Noise Cancellation Technique for -62dB Noise Suppression and 90.1% Efficiency.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
An Energy Recycling Envelope Tracking Supply Modulator Assisted by Small Cap Replica With 89.7% Efficiency and 37% Reduced Linear Amplifier Current for 150 MHz Bandwidth 5G New Radio RF Applications.
IEEE J. Solid State Circuits, 2022

Object Pose Estimation and Feature Extraction Based on PVNet.
IEEE Access, 2022

A Galvanic-Free Secondary-Side Control Flyback Converter with Digital Adaptive On-Time Control and Direct Sequence Spread Spectrum Technique for 15.5% Error Recovery Rate Improvement.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022


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