Yifan Zhao
Orcid: 0000-0001-7304-8206Affiliations:
- Fudan University, School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Shanghai, China
According to our database1,
Yifan Zhao authored at least 11 papers
between 2021 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
RAEnc: A Stall-Less Metadata Compression Framework for Return Address Integrity on High-Performance Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst., April, 2026
25.2 A 28nm 0.48mJ/boot Torus FHE Processor for Arbitrary Computation on Encrypted Data.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
DNA-HHE: Dual-mode Near-network Accelerator for Hybrid Homomorphic Encryption on the Edge.
CoRR, December, 2025
ARV-Q: An Adaptive RISC-V Vector Processor for Unified Support of Post-Quantum Standards and Side-Channel Protection on the Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
Sliding-Window Scheduling to Exploit Hybrid-Bonding-Based Accelerators for Fully Homomorphic Encryption.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
2024
RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital Signature.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
General Vector Instruction Extension for GF(2<sup>m</sup>) Polynomial Operation in Post-quantum Cryptography.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023
2022
A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021