Ziyi Hao

According to our database, Ziyi Hao authored at least 4 papers between 2015 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.

Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.

Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi

Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2016

EDSU: Error detection and sampling unified flip-flop with ultra-low overhead.

Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan

IEICE Electron. Express, 2016

2015

A timing failure tolerance design with in-field simultaneous error detection and correction.

Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015