Yimin Wang

Orcid: 0009-0008-7292-0670

Affiliations:
  • National University of Singapore, Singapore


According to our database1, Yimin Wang authored at least 12 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
JADE: Joint Architecture-Dataflow Exploration for LLM Inference on Heterogeneous In- and Near-Memory Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2026

Cross-Layer Evaluation for On-Chip Training of BEOL FeTFT-based CIM M3D Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

Topology-Mapping Co-Design for Scalable LLM Accelerators with Hierarchical Mesh-of-Trees NoC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

PRIMAL: Processing-In-Memory based Low-Rank Adaptation for LLM Inference Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration.
CoRR, November, 2025

LEAP: LLM Inference on Scalable PIM-NoC Architecture with Balanced Dataflow and Fine-Grained Parallelism.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024
Analysis of Higher-Order Ising Hamiltonians.
CoRR, 2024

Transposable Memory Based on the Ferroelectric Field-Effect Transistor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Energy-Efficient Ising Machines Using Capacitance-Coupled Latches for MaxCut Solving.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Design Framework for Ising Machines with Bistable Latch-Based Spins and All-to-All Resistive Coupling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Benchmarking DNN Mapping Methods for the in-Memory Computing Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

2021
Design Framework for SRAM-Based Computing-In-Memory Edge CNN Accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021


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