Xuanyao Fong

Orcid: 0000-0001-5939-7389

According to our database1, Xuanyao Fong authored at least 41 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Transposable Memory Based on the Ferroelectric Field-Effect Transistor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Energy-Efficient Ising Machines Using Capacitance-Coupled Latches for MaxCut Solving.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Design Framework for Ising Machines with Bistable Latch-Based Spins and All-to-All Resistive Coupling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Benchmarking DNN Mapping Methods for the in-Memory Computing Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Massively Parallel Continuous Local Search for Hybrid SAT Solving on GPUs.
CoRR, 2023

Energy-efficient superparamagnetic Ising machine and its application to traveling salesman problems.
CoRR, 2023

A Semi-Supervised Learning Method for Spiking Neural Networks Based on Pseudo-Labeling.
Proceedings of the International Joint Conference on Neural Networks, 2023

Domain-specific computing with non-volatile multi-terminal devices.
Proceedings of the International Conference on IC Design and Technology, 2023

2022
Electrical Tunable Spintronic Neuron with Trainable Activation Function.
CoRR, 2022

CITS: Coherent Ising Tree Search Algorithm Towards Solving Combinatorial Optimization Problems.
CoRR, 2022

An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Connection Pruning for Deep Spiking Neural Networks with On-Chip Learning.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021

Exchange-Coupling-Enabled Electrical-Isolation of Compute and Programming Paths in Valley-Spin Hall Effect based Spintronic Device for Neuromorphic Applications.
Proceedings of the Device Research Conference, 2021

2020
SIMBA: A Skyrmionic In-Memory Binary Neural Network Accelerator.
CoRR, 2020

Aggressive Leakage Current Reduction for Embedded MRAM Using Block-Level Power Gating.
Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020

2018
Domain Wall Motion-Based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions.
IEEE Trans. Biomed. Circuits Syst., 2018

Domain Wall Motion-based XOR-like Activation Unit With A Programmable Threshold.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2017
Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Spin-Transfer Torque Memories: Devices, Circuits, and Systems.
Proc. IEEE, 2016

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC.
ACM J. Emerg. Technol. Comput. Syst., 2016

High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell.
IEEE Trans. Inf. Forensics Secur., 2015

Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Exploring Spin Transfer Torque Devices for Unconventional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Device/circuit/architecture co-design of reliable STT-MRAM.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Approximate storage for energy efficient spintronic memories.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Design of robust spin-transfer torque magnetic random access memories for ultralow power high performance on-chip cache applications
PhD thesis, 2014

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity.
CoRR, 2014

Laser Induced Magnetization Reversal for Detection in Optical Interconnects.
CoRR, 2014

Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Dual pillar spin-transfer torque MRAMs for low power applications.
ACM J. Emerg. Technol. Comput. Syst., 2013

Reading spin-torque memory with spin-torque sensors.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2009
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2006
Analysis of super cut-off transistors for ultralow power digital logic circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006


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