Yiping Jia

According to our database, Yiping Jia authored at least 6 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Optimizing Off-Chip Memory Access for Deep Neural Network Accelerator.

Yong Zheng, Haigang Yang, Yi Shu, Yiping Jia, Zhihong Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

mTREE: A Customized Multicast-Enabled Tree-Based Network on Chip for AI Chips.

Yong Zheng, Haigang Yang, Yi Shu, Yiping Jia, Zhihong Huang

IEEE Embed. Syst. Lett., 2022

2021

A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS.

Binghui Wang, Haigang Yang, Yiping Jia

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019

A High Energy-Efficiency FPGA-Based LSTM Accelerator Architecture Design by Structured Pruning and Normalized Linear Quantization.

Yong Zheng, Haigang Yang, Zhihong Huang, Tianli Li, Yiping Jia

Proceedings of the International Conference on Field-Programmable Technology, 2019

Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGA.

Xinkai Di, Haigang Yang, Zhihong Huang, Ning Mao, Yiping Jia, Yong Zheng

Proceedings of the International Conference on Field-Programmable Technology, 2019

2013

A CMOS Field Programmable Analog Array for intelligent sensory application.

Xiaoyan Cheng, Tao Yin, Qisong Wu, Yiping Jia, Haigang Yang

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013