Yong-geol Kim

According to our database, Yong-geol Kim authored at least 4 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Logic-Embedded Flip-Flop Adapting Scan-Controlled Semidynamic and Clocked Domino Structures.

Min-Su Kim, Yong-geol Kim, Daeseong Lee, Hyoungwook Lee

Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

2024

An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-Low-Power Operations in 7nm Fin-FET Process.

Hyun-chul Hwang, Min-su Kim, Daeseong Lee, Yong-geol Kim, Byung-Su Kim, Kun-hyuk Kang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2018

Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling.

Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

Single-ended D flip-flop with implicit scan mux for high performance mobile AP.

Min-Su Kim, Chunghee Kim, Yong-geol Kim, Ah-Reum Kim, Jikyum Kim, Juhyun Kang, Daeseong Lee, Changjun Choi, Ilsuk Suh, Jungyul Pyo, Youngmin Shin, Jae Cheol Son

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016