Chunghee Kim

According to our database1, Chunghee Kim authored at least 11 papers between 1993 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
Single-ended D flip-flop with implicit scan mux for high performance mobile AP.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
Scan-controlled pulse flip-flops for mobile application processors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2008
Power and Skew Aware Point Diffusion Clock Network.
IEICE Trans. Electron., 2008

2000
Free MDD-Based Software Optimization Techniques for Embedded Systems.
Proceedings of the 2000 Design, 2000

1996
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
Performance-oriented technology mapping for LUT-based FPGA's.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Performance-driven circuit partitioning for prototyping by using multiple FPGA chips.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993
A simple yet effective technique for partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 1993

A combined hierarchical placement algorithm.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


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