Yongtae Kim
Orcid: 0000-0001-7039-973XAffiliations:
- Kyungpook National University, School of Computer Science and Engineering, Korea
- Intel Corporation, Santa Clara, CA, USA
- Texas A&M University, Department of Electrical and Computer Engineering, TX, USA
According to our database1,
Yongtae Kim authored at least 47 papers
between 2011 and 2026.
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Bibliography
2026
Design of Approximate Floating-Point Arithmetic Units Using Hardware-Efficient Rounding Schemes.
IEEE Embed. Syst. Lett., April, 2026
A Stride-based Sequence Aligner with Boundary-Aware Multi-Seed Traceback for Genomic DNA Sequence Analysis.
Proceedings of the 41st ACM/SIGAPP Symposium on Applied Computing, 2026
quEStab: Towards Scalable Quantum Circuit Simulation on Multi-GPU using an Extended Stabilizer Formalism.
Proceedings of the 40th ACM International Conference on Supercomputing, 2026
2025
Design of a Hardware-Efficient Approximate 4-2 Compressor for Multiplications in Image Processing.
IEEE Embed. Syst. Lett., August, 2025
Hardware-Efficient Quantized Stochastic Computing With Reduced Precision Stochastic Number Generator and LFSR-Based Counter.
Int. J. Circuit Theory Appl., 2025
Exploiting Omega Network and Inexact Accumulative Parallel Counter to Enhance Energy Efficiency in Stochastic Computing.
Proceedings of the 40th ACM/SIGAPP Symposium on Applied Computing, 2025
Can Less Accurate Be More Accurate? Surpassing Exact Multiplier with Approximate Design on NISQ Quantum Computers.
Proceedings of the 40th ACM/SIGAPP Symposium on Applied Computing, 2025
QQ: Is 2-bit Enough? Exploiting Quantization to Enhance Computation and Memory Efficiency in Quantum Simulation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025
Accuracy Performance Analysis of Quantized DNN Models Using Approximate 4-2 Compressor Based Multipliers.
Proceedings of the International Conference on Artificial Intelligence in Information and Communication, 2025
2024
Online Electric Vehicle Charging Strategy in Residential Areas With Limited Power Supply.
IEEE Trans. Smart Grid, May, 2024
A comprehensive exploration of approximate DNN models with a novel floating-point simulation framework.
Perform. Evaluation, 2024
Enabling Quantum Computer Simulation under Minimal Precision Floating-Point using Irrational Value Decomposition.
Proceedings of the 32nd International Conference on Modeling, 2024
Design of a Low-Cost Stochastic Computing-based Median Filter for Digital Image Processing.
Proceedings of the 21st International SoC Design Conference, 2024
Comparative Analysis of Quantum Adder Circuits in Computation Accuracy on Noisy Quantum Computers.
Proceedings of the 21st International SoC Design Conference, 2024
Design of an Efficient Parallel Random Number Generator Using a Single LFSR for Stochastic Computing.
Proceedings of the International Conference on Artificial Intelligence in Information and Communication , 2024
2023
IEEE Trans. Emerg. Top. Comput., 2023
TorchAxf: Enabling Rapid Simulation of Approximate DNN Models Using GPU-Based Floating-Point Computing Framework.
Proceedings of the 31st International Symposium on Modeling, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Enhancing Stochastic Computing using a Novel Hybrid Random Number Generator Integrating LFSR and Halton Sequence.
Proceedings of the 20th International SoC Design Conference, 2023
A Smith-Waterman Hardware Accelerator Design using Sliding Window for Genomic Sequence Alignment.
Proceedings of the 20th International SoC Design Conference, 2023
Towards Quantized Stochastic Computing by Leveraging Reduced Precision Binary Numbers through Bit Truncation.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Novel Efficient Approximate Adder Design using Single Input Pair based Computation.
Proceedings of the 19th International SoC Design Conference, 2022
An Accurate and Efficient Stochastic Computing Adder Exploiting Bit Shuffle Control Scheme.
Proceedings of the 19th International SoC Design Conference, 2022
Do Not Forget: Exploiting Stability-Plasticity Dilemma to Expedite Unsupervised SNN Training for Neuromorphic Processors.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
Low-Power Cross-Layer Error Management Using MIMO-LDPC Iterative Decoding for Video Processing.
IEEE Access, 2021
A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation.
IEEE Access, 2021
IEEE Access, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Training and Inference using Approximate Floating-Point Arithmetic for Energy Efficient Spiking Neural Network Processors.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
2020
IEICE Electron. Express, 2020
A Novel ReRAM-Based Architecture of Field Sequential Color Driver for High-Resolution LCoS Displays.
IEEE Access, 2020
Recent Trend of Neuromorphic Computing Hardware: Intel's Neuromorphic System Perspective.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
2019
A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Access, 2019
2016
Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration.
ACM J. Emerg. Technol. Comput. Syst., 2016
2015
A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing.
ACM J. Emerg. Technol. Comput. Syst., 2015
2013
A 0.38 V near/sub-V<sub>T</sub> digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process.
IET Circuits Devices Syst., 2013
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2012
A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning.
Proceedings of the IEEE 25th International SOC Conference, 2012
An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
High effective-resolution built-in jitter characterization with quantization noise shaping.
Proceedings of the 48th Design Automation Conference, 2011