Chulwoo Kim
Orcid: 0000-0003-4379-7905
According to our database1,
Chulwoo Kim
authored at least 188 papers
between 1999 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Ind. Electron., May, 2024
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.
IEEE J. Solid State Circuits, April, 2024
A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications.
IEEE J. Solid State Circuits, February, 2024
2023
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
A Thermoelectric Energy-Harvesting Interface With Dual-Conversion Reconfigurable DC-DC Converter and Instantaneous Linear Extrapolation MPPT Method.
IEEE J. Solid State Circuits, 2023
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces.
IEEE J. Solid State Circuits, 2023
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits, 2023
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations.
IEEE J. Solid State Circuits, 2022
IEEE J. Solid State Circuits, 2022
An Output-Boosted 3-ratio Switched-Capacitor DC-DC Converter with 0.5-to-1.8 V Output Voltage Range for Low-Power IoT Applications.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A 97.9% Peak Efficiency 9 V Output Three-Switch Hybrid Buck-Boost Power Stage Using 5 V CMOS.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Experimental Demonstration of RoFSO Transmission Combining WLAN Standard and WDM-FSO over 100m Distance.
Proceedings of the IEEE INFOCOM 2022, 2022
2021
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE J. Solid State Circuits, 2021
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.
IEEE J. Solid State Circuits, 2021
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications.
IEEE J. Solid State Circuits, 2021
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode.
IEEE J. Solid State Circuits, 2021
A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme.
IEEE J. Solid State Circuits, 2021
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.
IEEE Access, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Hybrid DC-DC Converter Capable of Supplying Heavy Load in Step-Up and Step-Down Mode.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications.
IEEE Trans. Circuits Syst., 2020
An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier.
IEEE J. Solid State Circuits, 2020
A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efficiency for Triboelectric Energy-Harvesting Applications.
IEEE J. Solid State Circuits, 2020
A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance.
IEEE J. Solid State Circuits, 2020
Near threshold voltage digital PLL using low voltage optimised blocks for AR display system.
IET Circuits Devices Syst., 2020
Proceedings of the International SoC Design Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits, 2019
A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries.
IEEE J. Solid State Circuits, 2019
A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 3D anthropometric sizing analysis system based on North American CAESAR 3D scan data for design of head wearable products.
Comput. Ind. Eng., 2018
A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC.
IEEE J. Solid State Circuits, 2017
3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop.
IEEE J. Solid State Circuits, 2017
A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system.
IEICE Electron. Express, 2017
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the Thirtieth International Florida Artificial Intelligence Research Society Conference, 2017
2016
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.
IEEE Trans. Very Large Scale Integr. Syst., 2016
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2016
An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the International SoC Design Conference, 2016
2015
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
D<sup>2</sup>ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing.
Microprocess. Microsystems, 2015
Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking Time.
IEEE J. Solid State Circuits, 2015
A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement.
IEEE J. Solid State Circuits, 2015
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
Springer Briefs in Electrical and Computer Engineering, Springer, ISBN: 978-3-319-02381-6, 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
23.7 Self-powered 30μW-to-10mW Piezoelectric energy-harvesting system with 9.09ms/V maximum power point tracking time.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the International Conference on Electronics, Information and Communications, 2014
A DC-DC boost converter with variation tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applications.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
A single-inductor 8-channel output DC-DC boost converter with time-limited power distribution control and single shared hysteresis comparator.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
366-kS/s 1.09-nJ 0.0013-${\rm mm}^{2}$ Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Single-Inductor Eight-Channel Output DC-DC Converter With Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A 0.008 mm<sup>2</sup> 500 µW 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface.
IEEE J. Solid State Circuits, 2013
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Robust transceiver based on worst-case SINR optimization for MIMO interfering broadcast channels with imperfect channel knowledge.
Proceedings of the 7th International Conference on Signal Processing and Communication Systems, 2013
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.
IEEE J. Solid State Circuits, 2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
IEEE J. Solid State Circuits, 2012
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.
IEEE J. Solid State Circuits, 2012
J. Circuits Syst. Comput., 2012
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 µs Frequency Acquisition Time.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Regulated Charge Pump With a Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.
IEEE J. Solid State Circuits, 2011
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 0.076mm<sup>2</sup> 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEICE Electron. Express, 2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A 7 ps Jitter 0.053 mm<sup>2</sup> Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC.
IEEE J. Solid State Circuits, 2009
A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
A 366kS/s 400uW 0.0013mm<sup>2</sup> frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 0.004-mm<sup>2</sup> Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEICE Electron. Express, 2008
A monolithic voltage-mode DC-DC converter with a novel oscillator and ramp generator.
IEICE Electron. Express, 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
Proceedings of the ESSCIRC 2008, 2008
A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
J. Circuits Syst. Comput., 2007
J. Circuits Syst. Comput., 2007
An automatic threshold-converged CMOS optical receiver for high-definition digital audio interfaces.
IEICE Electron. Express, 2007
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the Human-Computer Interaction. HCI Intelligent Multimodal Interaction Environments, 2007
Effect of Providing a Web-Based Collaboration Medium for Remote Customer Troubleshooting Tasks.
Proceedings of the Human Interface and the Management of Information. Interacting in Information Environments, 2007
Proceedings of the Human-Computer Interaction. Interaction Platforms and Techniques, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Evaluating and Improving a Self-Help Technical Support Web Site: Use of Focus Group Interviews.
Int. J. Hum. Comput. Interact., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006
2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the Embedded Software and Systems, Second International Conference, 2005
2004
IEEE J. Solid State Circuits, 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Proceedings of the OpenMP Shared Memory Parallel Programming, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the Integrated Circuit and System Design, 2003
2002
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
2001
PhD thesis, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999