Yoshiro Riho

According to our database, Yoshiro Riho authored at least 5 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2014

Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory.

Yoshiro Riho, Kazuo Nakazato

IEEE Trans. Very Large Scale Integr. Syst., 2014

A new DRAM architecture and its control method for the system power consumption.

Yoshiro Riho, Kazuo Nakazato

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

A new extension method of retention time for memory cell on dynamic random access memory.

Yoshiro Riho, Kazuo Nakazato

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2007

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme.

Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura

IEEE J. Solid State Circuits, 2007

2006

An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme.

Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006