Hitoshi Tanaka

Orcid: 0000-0003-1623-2650

According to our database1, Hitoshi Tanaka authored at least 16 papers between 1994 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Deep Learning-enabled Detection and Classification of Bacterial Colonies using a Thin Film Transistor (TFT) Image Sensor.
CoRR, 2022

2021
Using Hybrid Wavelet-Exponential Smoothing Approach for Streamflow Modeling.
Complex., 2021

Advanced Machine Learning Techniques for Predicting Nha Trang Shorelines.
IEEE Access, 2021

2015
A remark on two generalized Orlicz-Morrey spaces.
J. Approx. Theory, 2015

Influence of Polymer Gate Dielectrics on p-Channel and n-Channel Formation of Fluorene-type Polymer Light-emitting Transistors.
IEICE Trans. Electron., 2015

2011
Estimating damage-mitigation level of collision-prevention support braking.
Proceedings of the IEEE Intelligent Vehicles Symposium (IV), 2011

2007
Ultra-Low Voltage Nano-Scale Memories
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-68853-4, 2007

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme.
IEEE J. Solid State Circuits, 2007

2006
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications.
IEICE Trans. Electron., 2005

2003
A concepts-of-sentences associative neural network.
Syst. Comput. Jpn., 2003

Visualization of large-scale internal seiche in Lake Inawashiro.
J. Vis., 2003

1999
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits, 1999

1997
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip.
IEEE J. Solid State Circuits, 1997

1995
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits, November, 1995

1994
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1994


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