Young-Jae Min

Orcid: 0000-0002-0334-5560

According to our database1, Young-Jae Min authored at least 19 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2022
A Deep Learning Approach to Detect Anomalies in an Electric Power Steering System.
Sensors, 2022

A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores.
IEEE Access, 2022

2018
A unified DLL-controlled active rectifier in 6.78 MHz resonant-coupling wireless power receivers for space-limited portable and wearable applications.
IEICE Electron. Express, 2018

An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs.
IEICE Electron. Express, 2018

A novel secure simple Bluetooth pairing using physical vibration.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017
A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system.
IEICE Electron. Express, 2017

Erratum: Sub-1 V <i>V</i>-<i>I</i> converter-based voltage-controlled oscillator with a linear gain characteristic [IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170610].
IEICE Electron. Express, 2017

Sub-1 V <i>V</i>-<i>I</i> converter-based voltage-controlled oscillator with a linear gain characteristic.
IEICE Electron. Express, 2017

2016
All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2013
A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Design of Wavelet-Based ECG Detector for Implantable Cardiac Pacemakers.
IEEE Trans. Biomed. Circuits Syst., 2013

2012
A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison.
J. Circuits Syst. Comput., 2012

2011
A Jitter and Power Analysis on DCO.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Low-power programmable divider with a shared counter for frequency synthesiser.
IET Circuits Devices Syst., 2011

2010
Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique.
IEICE Electron. Express, 2010

2008
The low-power and low-area PWM by light intensity for photoflash in 0.35-µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 2.5-V 4-µW Low-Power Delta-Sigma Modulator for Implantable Cardiac Pacemaker with Periodic Bias Current Reduction Technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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