Won Ho Choi

Orcid: 0000-0002-7814-339X

According to our database1, Won Ho Choi authored at least 15 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2020
A Mott Insulator-Based Oscillator Circuit for Reservoir Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An In-Flash Binary Neural Network Accelerator with SLC NAND Flash Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Soft, Multi-DoF, Variable Stiffness Mechanism Using Layer Jamming for Wearable Robots.
IEEE Robotics Autom. Lett., 2019

A Binarized Neural Network Accelerator with Differential Crosspoint Memristor Array for Energy-Efficient MAC Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks.
Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019

On the Optimal Refresh Power Allocation for Energy-Efficient Memories.
Proceedings of the 2019 IEEE Global Communications Conference, 2019

2018
A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Improving Noise Tolerance of Hardware Accelerated Artificial Neural Networks.
Proceedings of the 17th IEEE International Conference on Machine Learning and Applications, 2018

2015
A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2008
The low-power and low-area PWM by light intensity for photoflash in 0.35-µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

1995
Design of a partially activated neural network.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995


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