Young-Kyun Cho

Orcid: 0000-0001-7803-3417

According to our database1, Young-Kyun Cho authored at least 12 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024
A Single Op-Amp Resonator-Based Continuous-Time Sigma-Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2023
Compact size buck converter using small output capacitance with pole-tuning technique.
Microelectron. J., 2023

2022
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2018
A Low-Power Continuous-Time Delta-Sigma Modulator Using a Resonant Single Op-Amp Third-Order Loop Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2015
Compensation technique for time alignment of envelope and phase paths in an envelope delta-sigma modulator.
IEICE Electron. Express, 2015

2012
20-MHz bandwidth continuous-time delta-sigma modulator for EPWM transmitter.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

A 9-bit 100-MS/s flash-SAR ADC without track-and-hold circuits.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

2011
A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique.
Microelectron. J., 2011

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications.
Microelectron. J., 2011

2010
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 9.15mW 0.22mm<sup>2</sup> 10b 204MS/s pipelined SAR ADC in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009


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