Young-Deuk Jeon

According to our database¹, Young-Deuk Jeon authored at least 17 papers between 2000 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2023

DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2023

Chiplet Heterogeneous-Integration AI Processor.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2019

Design of Analog and Digital Hybrid MAC Circuit for Artificial Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2012

A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique.

[BibT_eX]

[DOI]

Microelectron. J., 2011

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications.

[BibT_eX]

[DOI]

Microelectron. J., 2011

A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

2010

A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 9.15mW 0.22mm<sup>2</sup> 10b 204MS/s pipelined SAR ADC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007

A 10-bit 205-MS/s 1.0-mm<sup>2</sup> 90-nm CMOS Pipeline ADC for Flat Panel Display Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2000

Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Young-Deuk Jeon

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