Youngpyo Joo

Orcid: 0000-0003-4391-6361

Affiliations:
  • SK Hynix Inc, Icheon, South Korea
  • Samsung Electronics Limited, Gyeonggi, South Korea
  • Seoul National University, School of EECS, CAP Laboratory, Seoul, South Korea (PhD 2010)


According to our database1, Youngpyo Joo authored at least 8 papers between 2006 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2025
HPU: High-Bandwidth Processing Unit for Scalable, Cost-effective LLM Inference via GPU Co-processing.
CoRR, April, 2025

Improving Key-Value Cache Performance With Heterogeneous Memory Tiering: A Case Study of Compute-Express-Link-Based Memory Expansion.
IEEE Micro, 2025

2023
System Optimization of Data Analytics Platforms using Compute Express Link (CXL) Memory.
Proceedings of the IEEE International Conference on Big Data and Smart Computing, 2023

2012
Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC.
Des. Autom. Embed. Syst., 2012

2011
Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2009
On-chip communication architecture exploration for processor-pool-based MPSoC.
Proceedings of the Design, Automation and Test in Europe, 2009

2007
PeaCE: A hardware-software codesign environment for multimedia embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2007

2006
Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006


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