Hyungsoo Kim
According to our database1,
Hyungsoo Kim
authored at least 16 papers
between 2005 and 2023.
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Bibliography
2023
System Optimization of Data Analytics Platforms using Compute Express Link (CXL) Memory.
Proceedings of the IEEE International Conference on Big Data and Smart Computing, 2023
2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022
Proceedings of the 30th International Conference on Software, 2022
2021
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.
IEEE J. Solid State Circuits, 2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Design and Implementation of Quantum Key Distribution Network Control and Management.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2021
2017
23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications.
Proceedings of the Symposium on VLSI Circuits, 2015
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2012
A 1.2V 23nm 6F<sup>2</sup> 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 14th Asia-Pacific Network Operations and Management Symposium, 2012
2009
Proceedings of the 2009 IEEE Wireless Communications and Networking Conference, 2009
2008
Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network.
IEICE Trans. Electron., 2008
2006
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.
IEEE J. Solid State Circuits, 2006
2005
Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005