Yu-Hsiang Kao

According to our database1, Yu-Hsiang Kao authored at least 7 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
An iterative re-weighted least squares processor design for deblurring parabolic camera images.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

Queue-based segmentation algorithm for refining depth maps in light field camera applications.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2014
Design of a Bufferless Photonic Clos Network-on-Chip Architecture.
IEEE Trans. Computers, 2014

2011
CNoC: High-Radix Clos Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

BLOCON: A Bufferless Photonic Clos network-on-chip architecture.
Proceedings of the NOCS 2011, 2011

2010
Design of High-Radix Clos Network-on-Chip.
Proceedings of the NOCS 2010, 2010

2008
Cycle-time-aware sequential way-access set-associative cache for low energy consumption.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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