Juinn-Dar Huang
Orcid: 0000-0001-5961-7863
According to our database1,
Juinn-Dar Huang
authored at least 82 papers
between 1995 and 2023.
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Bibliography
2023
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization.
ACM Trans. Design Autom. Electr. Syst., March, 2023
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Hardware-Friendly Activation Function Designs and Its Efficient VLSI Implementations for Transformer-Based Applications.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Capture the Devil in the Details via Partition-then-Ensemble on Higher Resolution Images.
Proceedings of the Diabetic Foot Ulcers Grand Challenge - Third Challenge, 2022
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model.
ACM J. Emerg. Technol. Comput. Syst., 2021
All-You-Can-Fit 8-Bit Flexible Floating-Point Format for Accurate and Memory-Efficient Inference of Deep Neural Networks.
CoRR, 2021
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips.
ACM Trans. Design Autom. Electr. Syst., 2019
Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
2016
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints.
ACM J. Emerg. Technol. Comput. Syst., 2016
Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Reactant cost minimization through target concentration selection on microfluidic biochips.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Chain-based pin count minimization for general-purpose digital microfluidic biochips.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays.
Proceedings of the VLSI Design, Automation and Test, 2015
Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
J. Inf. Sci. Eng., 2014
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Latency-optimization synthesis with module selection for digital microfluidic biochips.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2012
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
2011
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Architectural exploration of 3D FPGAs towards a better balance between area and delay.
Proceedings of the Design, Automation and Test in Europe, 2011
Equivalence checking of scheduling with speculative code transformations in high-level synthesis.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
J. Inf. Sci. Eng., 2010
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Expandable MDC-based FFT architecture and its generator for high-performance applications.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2009
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM.
IEEE Trans. Very Large Scale Integr. Syst., 2009
ACM Trans. Design Autom. Electr. Syst., 2009
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Cycle-time-aware sequential way-access set-associative cache for low energy consumption.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
FSM-based transaction-level functional coverage for interface compliance verification.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
2000
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2000
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
1995
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping.
Proceedings of the 32st Conference on Design Automation, 1995