Yu Lei

Orcid: 0000-0003-4321-0385

Affiliations:

Chinese Academy of Sciences, Shanghai Institute of Micro-System and Information Technology, State Key Laboratory of Functional Materials for Informatics, China

According to our database¹, Yu Lei authored at least 15 papers between 2015 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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Bibliography

2024

Auto-Configuration Write Scheme With Enhanced Reliability for 3-D Cross-Point PCM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023

A 1S1R Model with the Monte Carlo Function for Subthreshold Sensing Operation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

An Ultra-Low Quiescent Current Resistor-Less Power on Reset Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

BIST-Based Fault Diagnosis for PCM With Enhanced Test Scheme and Fault-Free Region Finding Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A self-start circuit with asymmetric inductors reconfigurable technology for dual-output boost converter for energy harvesting.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

2V/3 Bias Scheme with Enhanced Dynamic Read Performances for 3-D Cross Point PCM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Near-threshold SIDO DC-DC converter with a high-precision ZCD for phase change memory chip.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

2018

A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017

Capacitor-less LDR based on flipped voltage follower with dual-feedback loops.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Enhanced read performance for phase change memory using a reference column.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

2015

A smart primary side current sensing strategy for single stage isolated PFC controller.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Yu Lei

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