Houpeng Chen

Orcid: 0000-0002-5766-5746

According to our database1, Houpeng Chen authored at least 26 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Auto-Configuration Write Scheme With Enhanced Reliability for 3-D Cross-Point PCM.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023
A high PSR and high-precision current-mode bandgap reference with g<sub>m</sub> boost self-regulated structure.
Microelectron. J., December, 2023

A novel constant-g<sub>m</sub> rail-to-rail input stage for operational amplifiers.
IEICE Electron. Express, 2023

A 1S1R Model with the Monte Carlo Function for Subthreshold Sensing Operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
2022 roadmap on neuromorphic devices and applications research in China.
Neuromorph. Comput. Eng., December, 2022

Post-silicon nano-electronic device and its application in brain-inspired chips.
Frontiers Neurorobotics, September, 2022

Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory.
Sensors, 2022

2021
An Ultra-Low Quiescent Current Resistor-Less Power on Reset Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
BIST-Based Fault Diagnosis for PCM With Enhanced Test Scheme and Fault-Free Region Finding Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A self-start circuit with asymmetric inductors reconfigurable technology for dual-output boost converter for energy harvesting.
IEICE Electron. Express, 2020

2V/3 Bias Scheme with Enhanced Dynamic Read Performances for 3-D Cross Point PCM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Near-threshold SIDO DC-DC converter with a high-precision ZCD for phase change memory chip.
IEICE Electron. Express, 2019

2018
A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Design and security evaluation of PCM-based rPUF using cyclic refreshing strategy.
IEICE Electron. Express, 2018

2017
Capacitor-less LDR based on flipped voltage follower with dual-feedback loops.
IEICE Electron. Express, 2017

Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration.
IEICE Electron. Express, 2017

A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process.
IEICE Electron. Express, 2017

Enhanced read performance for phase change memory using a reference column.
IEICE Electron. Express, 2017

2015
Methods to speed up read operation in a 64 Mbit phase change memory chip.
IEICE Electron. Express, 2015

A smart primary side current sensing strategy for single stage isolated PFC controller.
IEICE Electron. Express, 2015

2014
A smart method of optimizing the read/write current on PCM array.
IEICE Electron. Express, 2014

A novel auxiliary-free zero inductor current detection scheme for step down non-isolated LED driver.
IEICE Electron. Express, 2014

Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations.
IEICE Electron. Express, 2014

2002
Variables Bounding Based Retiming Algorithm.
J. Comput. Sci. Technol., 2002


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