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Yu-Yun Dai

Orcid: 0000-0001-8058-0380

According to our database1, Yu-Yun Dai authored at least 5 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Verification and Synthesis of Clock-Gated Circuits.
[BibTeX]
[DOI]
Yu-Yun Dai
,
Robert K. Brayton
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Identifying Transparent Logic in Gate-Level Circuits.
[BibTeX]
[DOI]
Yu-Yun Dai
,
Robert K. Brayton
Proceedings of the Advanced Logic Synthesis, 2018

2017
Verification and Synthesis of Clock-Gated Circuits.
[BibTeX]
[DOI]
Yu-Yun Dai
PhD thesis, 2017

Circuit recognition with deep learning.
[BibTeX]
[DOI]
Yu-Yun Dai
,
Robert K. Brayton
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2015
Sequential equivalence checking of clock-gated circuits.
[BibTeX]
[DOI]
Yu-Yun Dai
,
Kei-Yong Khoo
,
Robert K. Brayton
Proceedings of the 52nd Annual Design Automation Conference, 2015


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