Robert K. Brayton

According to our database1, Robert K. Brayton
  • authored at least 300 papers between 1963 and 2017.
  • has a "Dijkstra number"2 of three.

Awards

IEEE Fellow

IEEE Fellow 1981, "For pioneering work in the theory of nonlinear networks, stability theory, and sparse matrix techniques.".

Timeline

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Bibliography

2017
Circuit recognition with deep learning.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Property directed reachability with word-level abstraction.
Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

Fast-extract with cube hashing.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
m-Inductive Property of Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

2QBF: Challenges and Solutions.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Efficient uninterpreted function abstraction and refinement for word-level model checking.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

2015
Component-Based Design by Solving Language Equations.
Proceedings of the IEEE, 2015

Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue].
Proceedings of the IEEE, 2015

Automated Synthesis of Protocol Converters with BALM-II.
Proceedings of the Software Engineering and Formal Methods, 2015

Technology Mapping into General Programmable Cells.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Reverse Engineering with Simulation Graphs.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Bi-Decomposition Using Boolean Relations.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Sequential equivalence checking of clock-gated circuits.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Sequential Equivalence Checking for Clock-Gated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract).
Proceedings of the 5th ACM Conference on Bioinformatics, 2014

ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Ranking structure in communication fabrics.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

LEC: Learning Driven Data-path Equivalence Checking.
Proceedings of the Second International Workshop on Design and Implementation of Formal Tools and Systems, 2013

A semi-canonical form for sequential AIGs.
Proceedings of the Design, Automation and Test in Europe, 2013

GLA: gate-level abstraction revisited.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Mapping into LUT structures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Scalable progress verification in credit-based flow-control systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Scalable don't-care-based logic optimization and resynthesis.
TRETS, 2011

Automating Logic Transformations With Approximate SPFDs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Delay optimization using SOP balancing.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Enhancing ABC for stabilization verification of SystemVerilog/VHDL models.
Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, 2011

Efficient implementation of property directed reachability.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010
NSF Workshop on EDA: Past, Present, and Future (Part 2).
IEEE Design & Test of Computers, 2010

NSF Workshop on EDA: Past, Present, and Future (Part 1).
IEEE Design & Test of Computers, 2010

Global delay optimization using structural choices.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Combinational techniques for sequential equivalence checking.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

ABC: An Academic Industrial-Strength Verification Tool.
Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009
Scalable don't-care-based logic optimization and resynthesis.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

SmartOpt: an industrial strength framework for logic synthesis.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Sequential logic rectifications with approximate SPFDs.
Proceedings of the Design, Automation and Test in Europe, 2009

Speculative reduction-based scalable redundancy identification.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Compositionally Progressive Solutions of Synchronous FSM Equations.
Discrete Event Dynamic Systems, 2008

Placement based multiplier rewiring for cell-based designs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Scalable and scalably-verifiable sequential synthesis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Boolean factoring and decomposition of logic networks.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Recording Synthesis History for Sequential Verification.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

Invariant-Strengthened Elimination of Dependent State Elements.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

Scalable min-register retiming under timing and initializability constraints.
Proceedings of the 45th Design Automation Conference, 2008

Merging nodes under sequential observability.
Proceedings of the 45th Design Automation Conference, 2008

2007
Improvements to Technology Mapping for LUT-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Efficient Solution of Language Equations Using Partitioned Representations
CoRR, 2007

SAT-Based Complete Don't-Care Computation for Network Optimization
CoRR, 2007

Semi-detailed bus routing with variation reduction.
Proceedings of the 2007 International Symposium on Physical Design, 2007

A simultaneous bus orientation and bused pin flipping algorithm.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Combinational and sequential mapping with priority cuts.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A new algorithm for the largest compositionally progressive solution of synchronous language equations.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Fast Minimum-Register Retiming via Binary Maximum-Flow.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Automated Extraction of Inductive Invariants to Aid Model Checking.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

On Resolution Proofs for Combinational Equivalence.
Proceedings of the 44th Design Automation Conference, 2007

Automating Logic Rectification by Approximate SPFDs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Using simulation and satisfiability to compute flexibilities in Boolean networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A theory of nondeterministic networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Retiming and Resynthesis: A Complexity Perspective.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Reducing Structural Bias in Technology Mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Improvements to combinational equivalence checking.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Factor cuts.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Improvements to technology mapping for LUT-based FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.
Proceedings of the 43rd Design Automation Conference, 2006

DAG-aware AIG rewriting a fresh look at combinational logic synthesis.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Synthesis methodology for built-in at-speed testing.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Reducing structural bias in technology mapping.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Efficient Solution of Language Equations Using Partitioned Representations.
Proceedings of the 2005 Design, 2005

SAT-Based Complete Don't-Care Computation for Network Optimization.
Proceedings of the 2005 Design, 2005

Gaining Predictability and Noise Immunity in Global Interconnects.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
SPFD-based wire removal in standard-cell and network-of-PLA circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

On breakable cyclic definitions.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A new incremental placement algorithm and its application to congestion-aware divisor extraction.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A timing-driven module-based chip design flow.
Proceedings of the 41th Design Automation Conference, 2004

Functional Dependency for Verification Reduction.
Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003
Sequential optimization in the absence of global reset.
ACM Trans. Design Autom. Electr. Syst., 2003

PLA-based regular structures and their synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

On the verification of sequential equivalence.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Fishbone: a block-level placement and routing scheme.
Proceedings of the 2003 International Symposium on Physical Design, 2003

A Theory of Non-Deterministic Networks.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
Proceedings of the 2003 Design, 2003

Reducing Multi-Valued Algebraic Operations to Binary.
Proceedings of the 2003 Design, 2003

Generalized cofactoring for logic function evaluation.
Proceedings of the 40th Design Automation Conference, 2003

Don't cares in logic minimization of extended finite state machines.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Formula-Dependent Equivalence for Compositional CTL Model Checking.
Formal Methods in System Design, 2002

Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
IWLS, 2002

Topologically Constrained Logic Synthesis.
IWLS, 2002

Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design.
IWLS, 2002

Simplification of Non-Deterministic Multi-Valued Networks.
IWLS, 2002

A Boolean Paradigm in Multi-Valued Logic Synthesis.
IWLS, 2002

Reducing Multi-Valued Algebraic Operations to Binary.
IWLS, 2002

Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic.
IWLS, 2002

On the Verification of Sequential Equivalence.
IWLS, 2002

Optimization of Multi-Valued Multi-Level Networks.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Topologically constrained logic synthesis.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Whirlpool PLAs: a regular logic structure and their synthesis.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Simplification of non-deterministic multi-valued networks.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Using Problem Symmetry in Search Based Satisfiability Algorithms.
Proceedings of the 2002 Design, 2002

River PLAs: a regular circuit structure.
Proceedings of the 39th Design Automation Conference, 2002

Software synthesis from synchronous specifications using logic simulation techniques.
Proceedings of the 39th Design Automation Conference, 2002

HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Theory of safe replacements for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Partial-Order Reduction in Symbolic State-Space Exploration.
Formal Methods in System Design, 2001

A Timing-Driven Macro-Cell Placement Algorithm.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Solution of Parallel Language Equations for Logic Synthesis.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Sequential SPFDs.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A Force-Directed Maze Router.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Compatible Observability Don't Cares Revisited.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Using SAT for combinational equivalence checking.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Logic optimization and code generation for embedded control applications.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Model-checking continous-time Markov chains.
ACM Trans. Comput. Log., 2000

Negative thinking in branch-and-bound: the case of unate covering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Sequential synthesis using S1S.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Integration of retiming with architectural floorplanning.
Integration, 2000

Performance planning.
Integration, 2000

Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks.
Formal Methods in System Design, 2000

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A Force-Directed Macro-Cell Placer.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Don't Cares and Multi-Valued Logic Network Minimization.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Area and search space control for technology mapping.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Sequential Multi-Valued Network Simplification using Redundancy Removal.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Multi-Valued Logic Synthesis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.
Proceedings of the VLSI: Systems on a Chip, 1999

Timing-safe false path removal for combinational modules.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Probabilistic state space search.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Using Combinational Verification for Sequential Circuits.
Proceedings of the 1999 Design, 1999

Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints.
Proceedings of the 36th Conference on Design Automation, 1999

A Novel VLSI Layout Fabric for Deep Sub-Micron Applications.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Theory and algorithms for face hypercube embedding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Efficient Verification and Synthesis using Design Commonalities.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Implementation and use of SPFDs in optimizing Boolean networks.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

On the optimization power of retiming and resynthesis transformations.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Wireplanning in logic synthesis.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Combinational Verification based on High-Level Functional Specifications.
Proceedings of the 1998 Design, 1998

Planning for Performance.
Proceedings of the 35th Conference on Design Automation, 1998

Delay-Optimal Technology Mapping by DAG Covering.
Proceedings of the 35th Conference on Design Automation, 1998

Hierarchical Functional Timing Analysis.
Proceedings of the 35th Conference on Design Automation, 1998

Structural Symmetry and Model Checking.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

A New Low-Cost Method for Identifying Untestable Path Delay Faults.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Symbolic two-level minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Explicit and implicit algorithms for binate covering problems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Theory and algorithms for state minimization of nondeterministic FSMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Implicit computation of compatible sets for state minimization of ISFSMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Efficient Identification of Non-Robustly Untestable Path Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Timed Binary Decision Diagrams.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Reachability analysis using partitioned-ROBDDs.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Sequential optimisation without state space exploration.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Approximate timing analysis of combinational circuits under the XBD0 model.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A fast and robust exact algorithm for face embedding.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Negative thinking by incremental problem solving: application to unate covering.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Exact Required Time Analysis via False Path Detection.
Proceedings of the 34st Conference on Design Automation, 1997

STARI: A Case Study in Compositional and Hierarchical Timing Verification.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

Partial-Order Reduction in Symbolic State Space Exploration.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

1996
Permissible functions for multioutput components in combinational logic optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Combinational test generation using satisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Valid clock frequencies and their computation in wavepipelined circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

A study of composition schemes for mixed apply/compose based construction of ROBDDs.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Binary decision diagrams on network of workstation.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Latch Redundancy Removal Without Global Reset.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Early Quantification and Partitioned Transition Relations.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

The case for retiming with explicit reset circuitry.
ICCAD, 1996

Decomposition Techniques for Efficient ROBDD Construction.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Verification Using Uninterpreted Functions and Finite Instantiations.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996


Incremental re-encoding for symbolic traversal of product machines.
Proceedings of the conference on European design automation, 1996

High Performance BDD Package By Exploiting Memory Hiercharchy.
Proceedings of the 33st Conference on Design Automation, 1996

Engineering Change in a Non-Deterministic FSM Setting.
Proceedings of the 33st Conference on Design Automation, 1996

Verifying Abstractions of Timed Systems.
Proceedings of the CONCUR '96, 1996


Verifying Continuous Time Markov Chains.
Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995
Testing Language Containment for omega-Automata Using BDD's
Inf. Comput., April, 1995

An efficient heuristic procedure for solving the state assignment problem for event-based specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Delay fault coverage, test set size, and performance trade-offs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Network Hierarchies and Node Minimization.
IEICE Transactions, 1995

An Environment for Formal Verification Based on Symbolic Computations.
Formal Methods in System Design, 1995

Functional clock schedule optimization.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Structural Complexity of Omega-Automata.
STACS, 1995

Power-Up Delay for Retiming Digital Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Incremental methods for FSM traversal.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Implicit state minimization of non-deterministic FSMs.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Multi-level logic optimization of FSM networks.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Sequential synthesis using S1S.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Exploiting power-up delay for sequential optimization.
Proceedings of the Proceedings EURO-DAC'95, 1995

Decomposition of logic functions for minimum transition activity.
Proceedings of the 1995 European Design and Test Conference, 1995

The Validity of Retiming Sequential Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Language containment of non-deterministic omega-automata.
Proceedings of the Correct Hardware Design and Verification Methods, 1995

The Rabin Index and Chain Automata, with Applications to Automatas and Games.
Proceedings of the Computer Aided Verification, 1995

Automatic Datapath Abstraction In Hardware Systems.
Proceedings of the Computer Aided Verification, 1995

Supervisory Control of Finite State Machines.
Proceedings of the Computer Aided Verification, 1995

1994
Specification, synthesis, and verification of hazard-free asynchronous circuits.
VLSI Signal Processing, 1994

Satisfaction of input and output encoding constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Circuit structure relations to redundancy and delay.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Deterministic w Automata vis-a-vis Deterministic Buchi Automata.
Proceedings of the Algorithms and Computation, 5th International Symposium, 1994

An Exact Optimization of Two-Level Acyclic Sequential Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Incremental formal design verification.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Multi-level synthesis for safe replaceability.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A redesign technique for combinational circuits based on gate reconnections.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Equivalences for Fair Kripke Structures.
Proceedings of the Automata, Languages and Programming, 21st International Colloquium, 1994

State Minimization of Pseudo Non-Deterministic FSM's.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Permissible Observability Relations in FSM Networks.
Proceedings of the 31st Conference on Design Automation, 1994

Heuristic Minimization of BDDs Using Don't Cares.
Proceedings of the 31st Conference on Design Automation, 1994

Performance Optimization Using Exact Sensitization.
Proceedings of the 31st Conference on Design Automation, 1994

Optimum Functional Decomposition Using Encoding.
Proceedings of the 31st Conference on Design Automation, 1994

Exact Minimum Cycle Times for Finite State Machines.
Proceedings of the 31st Conference on Design Automation, 1994

A Fully Implicit Algorithm for Exact State Minimization.
Proceedings of the 31st Conference on Design Automation, 1994

BDD Variable Ordering for Interacting Finite State Machines.
Proceedings of the 31st Conference on Design Automation, 1994

HSIS: A BDD-Based Environment for Formal Verification.
Proceedings of the 31st Conference on Design Automation, 1994

Criteria for the Simple Path Property in Timed Automata.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

Improving Language Containment Using Fairness Graphs.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1993
ESPRESSO-SIGNATURE: a new exact minimizer for logic functions.
IEEE Trans. VLSI Syst., 1993

Heuristic minimization of multiple-valued relations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Computing the initial states of retimed circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Two-Level Minimization of Multivalued Functions with Large Offsets.
IEEE Trans. Computers, 1993

Minimization of Logic Functions Using Essential Signature Sets.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Logic Optimization with Multi-Output Gates.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Physically Realizable Gate Models.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Heuristic Minimization of Synchronous Relations.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Some Results on the Complexity of Boolean Functions for Table Look Up Architectures.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

The maximum set of permissible behaviors for FSM networks.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Input don't care sequences in FSM networks.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Minimum padding to satisfy short path constraints.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Cube-packing and two-level minimization.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Dynamic variable reordering for BDD minimization.
Proceedings of the European Design Automation Conference 1993, 1993

Resynthesis of Multi-Phase Pipelines.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Sequential Synthesis for Table Look Up Programmable Gate Arrays.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Elimination of Dynamic hazards by Factoring.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Espresso-Signature: A New Exact Minimizer for Logic Functions.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

On Computing the Transitive Closure of a State Transition Relation.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Delay Fault Coverage and Performance Tradeoffs.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

A Unified Approach to Language Containment and Fair CTL Model Checking.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Alternating RQ Timed Automata.
Proceedings of the Computer Aided Verification, 5th International Conference, 1993

BDD-Based Debugging Of Design Using Language Containment and Fair CTL.
Proceedings of the Computer Aided Verification, 5th International Conference, 1993

Logic Synthesis and Design Verification.
Proceedings of the Computer Aided Verification, 5th International Conference, 1993

1992
Symbolic minimization of multilevel logic and the input encoding problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Sequential Circuit Design Using Synthesis and Optimization.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

On Relationship Between ITE and BDD.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Delay Prediction for Technology-Independent Logic Equations.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Graph algorithms for clock schedule optimization.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Valid clocking in wavepipelined circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Automatic compositional minimization in CTL model checking.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Boolean matching in logic synthesis.
Proceedings of the conference on European design automation, 1992

On the Temporal Equivalence of Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited.
Proceedings of the 29th Design Automation Conference, 1992

Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation.
Proceedings of the 29th Design Automation Conference, 1992

An Improved Synthesis Algorithm for Multiplexor-Based PGA's.
Proceedings of the 29th Design Automation Conference, 1992

Solving the State Assignment Problem for Signal Transition Graphs.
Proceedings of the 29th Design Automation Conference, 1992

Automatic Reduction in CTL Compositional Model Checking.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

Efficient omega-Regular Language Containment.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991
Retiming and resynthesis: optimizing sequential networks with combinational techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Reduced offsets for minimization of binary-valued functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Preserving Don't Care Conditions During Retiming.
VLSI, 1991

Incremental Synthesis for Engineering Changes.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Retiming of Circuits with Single Phase Transparent Latches.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Three-Level Decomposition with Application to PLDs.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Heuristic Minimazation of Multiple-Valued Relations.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Extracting Local Don't Cares for Network Optimization.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Observability Relations and Observability Don't Cares.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Improved Logic Synthesis Algorithms for Table Look Up Architectures.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On Clustering for Minimum Delay/Area.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Performance Enhancement through the Generalized Bypass Transform.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Framework for Satisfying Input and Output Encoding Constraints.
Proceedings of the 28th Design Automation Conference, 1991

1990
The observability don't-care set and its approximations.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Implicit State Enumeration of Finite State Machines Using BDDs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Algorithms for Discrete Function Manipulation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Timing Optimization with Testability Considerations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Performance Optimization of Pipelined Circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Logic Synthesis for Programmable Gate Arrays.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Timing Analysis in Precharge/Unate Networks.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Reduced Offsets for Two-Level Multi-Valued Logic Minimization.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Fast two-level logic minimizers for multi-level logic synthesis.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Consistency and observability invariance in multi-level logic synthesis.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

An exact minimizer for Boolean relations.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

SLIP: a software environment for system level interactive partitioning.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Multi-level Logic Simplification Using Don't Cares and Filters.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Efficient Prime Factorization of Logic Expressions.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Multi-level logic minimization using implicit don't cares.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Timing optimization of combinational logic.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Logic verification using binary decision diagrams in a logic synthesis environment.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A modified approach to two-level logic minimization.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Don't cares and global flow analysis of Boolean networks.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

XPSim: a MOS VLSI simulator.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
MIS: A Multiple-Level Logic Optimization System.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

1986
Correction to "Optimal State Assignment for Finite State Machines".
IEEE Trans. on CAD of Integrated Circuits and Systems, 1986

1985
Optimal State Assignment for Finite State Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1985

1964
Stability Criteria for Large Networks.
IBM Journal of Research and Development, 1964

1963
An Analysis of the Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel-Diode Circuit.
IEEE Trans. Electronic Computers, 1963


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