Yuan Yao

Orcid: 0000-0001-7479-9263

Affiliations:

Harvard University, Cambridge, MA, USA
Zhejiang University, School of Computer Science and Technology, Hangzhou, China (PhD 2017)

According to our database¹, Yuan Yao authored at least 8 papers between 2013 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Article

PhD thesis

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Bibliography

2023

Early DSE and Automatic Generation of Coarse-grained Merged Accelerators.

[BibT_eX]

[DOI]

Iulian Brumar

Georgios Zacharopoulos

ACM Trans. Embed. Comput. Syst., March, 2023

2020

SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs.

[BibT_eX]

[DOI]

José Miguel Hernández-Lobato

Gu-Yeon Wei

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

2019

Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization.

[BibT_eX]

[DOI]

José Miguel Hernández-Lobato

Gu-Yeon Wei

IEEE Comput. Archit. Lett., 2019

2017

TC-Release++: An Efficient Timestamp-Based Coherence Protocol for Many-Core Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

2016

Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Supercomputing, 2016

2015

SelectDirectory: a selective directory for cache coherence in many-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013

FPGA based hardware-software co-designed dynamic binary translation system.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Yuan Yao

Timeline

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