Yuan Yao

Orcid: 0000-0001-9448-5595

Affiliations:
  • Uppsala University, Sweden
  • KTH Royal Institute of Technology, Stockholm, Sweden (former)


According to our database1, Yuan Yao authored at least 15 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
SE-CNN: Convolution Neural Network Acceleration via Symbolic Value Prediction.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core Processors.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

2021
TSOPER: Efficient Coherence-Based Strict Persistency.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS.
IEEE Trans. Computers, 2020

2018
Thread Voting DVFS for Manycore NoCs.
IEEE Trans. Computers, 2018

iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Dynamic Traffic Regulation in NoC-Based Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS.
IEEE Trans. Computers, 2017

Prediction based convolution neural network acceleration: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

2016
Aggregate Flow-Based Performance Fairness in CMPs.
ACM Trans. Archit. Code Optim., 2016

Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

DVFS for NoCs in CMPs: A thread voting approach.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Memory-access aware DVFS for network-on-chip in CMPs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
Towards stochastic delay bound analysis for Network-on-Chip.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014


  Loading...