Yuhang Liu

Orcid: 0000-0002-1699-3161

Affiliations:
  • Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Computer Architecture, Beijing, China


According to our database1, Yuhang Liu authored at least 18 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2024
Suppressing the Interference Within a Datacenter: Theorems, Metric and Strategy.
IEEE Trans. Parallel Distributed Syst., May, 2024

2023
Ah-Q: Quantifying and Handling the Interference within a Datacenter from a System Perspective.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2021
HCDA: from computational thinking to a generalized thinking paradigm.
Commun. ACM, 2021

LSP: Collective Cross-Page Prefetching for NVM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
IMPULP: A Hardware Approach for In-Process Memory Protection via User-Level Partitioning.
J. Comput. Sci. Technol., 2020

2019
LPM: A Systematic Methodology for Concurrent Data Access Pattern Optimization from a Matching Perspective.
IEEE Trans. Parallel Distributed Syst., 2019

Gene-Patterns: Should Architecture be Customized for Each Application?
CoRR, 2019

HCMA: Supporting High Concurrency of Memory Accesses with Scratchpad Memory in FPGAs.
Proceedings of the 2019 IEEE International Conference on Networking, 2019

Make Page Coloring more Efficient on Slice-Based Three-Level Cache.
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019

Characterizations and Architectural Implications of NVM's External DRAM Cache.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

2018
PTAT: An Efficient and Precise Tool for Tracing and Profiling Detailed TLB Misses.
ACM Trans. Embed. Comput. Syst., 2018

CaL: Extending Data Locality to Consider Concurrency for Performance Optimization.
IEEE Trans. Big Data, 2018

2017
Evaluating the Combined Effect of Memory Capacity and Concurrency for Many-Core Chip Design.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2017

PTAT: An efficient and precise tool for collecting detailed TLB miss traces.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Fine-Grained Data Committing for Persistent Memory.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

SMEFF: A scalable memory extension fabric for FPGA.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
Efficient design space exploration by knowledge transfer.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016


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