Tianyue Lu

Orcid: 0009-0001-8808-0935

According to our database1, Tianyue Lu authored at least 22 papers between 2013 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
ANIMo: Accelerating Nested Isolation with Monitor-free Domain Transition.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
CoroAMU: Unleashing Memory-Driven Coroutines through Latency-Aware Decoupled Operations.
CoRR, November, 2025

DASICS: Efficient In-Process Protection with Hardware-Assisted Dynamic Compartmentalization.
Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

2024
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access.
ACM Trans. Archit. Code Optim., September, 2024

2023
DASICS: Enhancing Memory Protection with Dynamic Compartmentalization.
CoRR, 2023

Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

HoPP: Hardware-Software Co-Designed Page Prefetching for Disaggregated Memory.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Rethinking Design Paradigm of Graph Processing System with a CXL-like Memory Semantic Fabric.
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023

2022
GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing.
Proceedings of the International Conference on Field-Programmable Technology, 2022

2021
Asynchronous Memory Access Unit for General Purpose Processors.
CoRR, 2021

LSP: Collective Cross-Page Prefetching for NVM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
System measurement of Intel AEP Optane DIMM.
CoRR, 2020

2019
Make Page Coloring more Efficient on Slice-Based Three-Level Cache.
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019

Characterizations and Architectural Implications of NVM's External DRAM Cache.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

2017
Fine-Grained Data Committing for Persistent Memory.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

2015
Twin-Load: Building a Scalable Memory System over the Non-Scalable Interface.
CoRR, 2015

2014
MIMS: Towards a Message Interface Based Memory System.
J. Comput. Sci. Technol., 2014

Achieving efficient packet-based memory system by exploiting correlation of memory requests.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
MIMS: Towards a Message Interface based Memory System
CoRR, 2013


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