Yuki Yoshikawa

According to our database, Yuki Yoshikawa authored at least 16 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Patchworking Multiple Pairwise Distances for Learning with Distance Matrices.

Ken Takano, Hideitsu Hino, Yuki Yoshikawa, Noboru Murata

Proceedings of the Latent Variable Analysis and Signal Separation, 2015

2013

A study of thermal sensation with visuo-thermal projection interfaces.

Yuki Yoshikawa, Daisuke Iwai, Kosuke Sato

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

A binding algorithm in high-level synthesis for path delay testability.

Yuki Yoshikawa

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2011

Hybrid Test Application in Partial Skewed-Load Scan Design.

Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

High-level synthesis for multi-cycle transient fault tolerant datapaths.

Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Test Compression Based on Lossy Image Encoding.

Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

A Practical Threshold Test Generation for Error Tolerant Application.

Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue

IEICE Trans. Inf. Syst., 2010

An FPGA-based fail-soft system with adaptive reconfiguration.

Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Hybrid test application in hybrid delay scan design.

Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 15th European Test Symposium, 2010

A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic.

Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009

A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification.

Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Reliability and Performance Analysis of FPGA-Based Fault Tolerant System.

Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A Practical Approach to Threshold Test Generation for Error Tolerant Circuits.

Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fast false path identification based on functional unsensitizability using RTL information.

Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2007

False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults.

Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 16th Asian Test Symposium, 2007

2005

Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.

Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005