Michiko Inoue

Orcid: 0000-0002-9837-5147

According to our database1, Michiko Inoue authored at least 123 papers between 1992 and 2024.

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Bibliography

2024
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024

2023
Ring exploration of myopic luminous robots with visibility more than one.
Inf. Comput., June, 2023

Eventually consistent distributed ledger despite degraded atomic broadcast.
Concurr. Comput. Pract. Exp., 2023

Meeting Times of Non-atomic Random Walks.
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2023

Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning.
Proceedings of the IEEE International Test Conference, 2023

Age group identification using gaze-guided feature extraction.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

Heatmap Overlay Using Neutral Body Model for Visualizing the Measured Gaze Distributions of Observers.
Proceedings of the Pattern Recognition - 7th Asian Conference, 2023

2022
Terminating Grid Exploration with Myopic Luminous Robots.
Int. J. Netw. Comput., 2022

Gender Recognition Using a Gaze-Guided Self-Attention Mechanism Robust Against Background Bias in Training Samples.
IEICE Trans. Inf. Syst., 2022

Weakly Byzantine Gathering with a Strong Team.
IEICE Trans. Inf. Syst., 2022

Systematic Unsupervised Recycled Field-Programmable Gate Array Detection.
CoRR, 2022

Brief Announcement: Gathering Despite a Linear Number of Weakly Byzantine Agents.
Proceedings of the PODC '22: ACM Symposium on Principles of Distributed Computing, Salerno, Italy, July 25, 2022

Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data.
Proceedings of the IEEE International Test Conference, 2022

Gathering despite a linear number of weakly Byzantine agents.
Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

Subjective Scores and Gaze Distribution in Personality Evaluations: Effect of Subjects' Clothing on Observers' Impressions of Them.
Proceedings of the Digital Human Modeling and Applications in Health, Safety, Ergonomics and Risk Management. Anthropometry, Human Behavior, and Communication, 2022

2021
Uniform bipartition in the population protocol model with arbitrary graphs.
Theor. Comput. Sci., 2021

Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Hardware-Software Co-Design for Decimal Multiplication.
Comput., 2021

Population Protocols for Graph Class Identification Problems.
Proceedings of the 25th International Conference on Principles of Distributed Systems, 2021

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process.
Proceedings of the IEEE International Test Conference, 2021

Study on High-Accuracy and Low-Cost Recycled FPGA Detection.
Proceedings of the IEEE International Test Conference, 2021

Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Gathering with a strong team in weakly Byzantine environments.
Proceedings of the ICDCN '21: International Conference on Distributed Computing and Networking, 2021

Body-Part Attention Probability for Measuring Gaze During Impression Word Evaluation.
Proceedings of the HCI International 2021 - Posters - 23rd HCI International Conference, 2021

Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020
Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Byzantine-Tolerant Gathering of Mobile Agents in Asynchronous Arbitrary Networks with Authenticated Whiteboards.
IEICE Trans. Inf. Syst., 2020

Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit.
J. Electron. Test., 2020

Gender Classification using the Gaze Distributions of Observers on Privacy-protected Training Images.
Proceedings of the 15th International Joint Conference on Computer Vision, 2020

Uniform Bipartition in the Population Protocol Model with Arbitrary Communication Graphs.
Proceedings of the 24th International Conference on Principles of Distributed Systems, 2020

Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
A Population Protocol for Uniform $k$-partition under Global Fairness.
Int. J. Netw. Comput., 2019

Space-Optimal Population Protocols for Uniform Bipartition Under Global Fairness.
IEICE Trans. Inf. Syst., 2019

Black Hole Search Despite Byzantine Agents.
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2019

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Uniform Partition in Population Protocol Model Under Weak Fairness.
Proceedings of the 23rd International Conference on Principles of Distributed Systems, 2019

Asian Test Symposium - Past, Present and Future -.
Proceedings of the IEEE International Test Conference, 2019

Low Cost Recycled FPGA Detection Using Virtual Probe Technique.
Proceedings of the IEEE International Test Conference in Asia, 2019

Classification of Trojan Nets Based on SCOAP Values using Supervised Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Eventually Consistent Distributed Ledger Relying on Degraded Atomic Broadcast.
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling.
Proceedings of the 24th IEEE European Test Symposium, 2019

Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Comparing the Recognition Accuracy of Humans and Deep Learning on a Simple Visual Inspection Task.
Proceedings of the Pattern Recognition - 5th Asian Conference, 2019

2018
Byzantine-Tolerant Gathering of Mobile Agents in Arbitrary Networks with Authenticated Whiteboards.
IEICE Trans. Inf. Syst., 2018

Gathering of Mobile Agents in Asynchronous Byzantine Environments with Authenticated Whiteboards.
Proceedings of the Networked Systems - 6th International Conference, 2018

Short Paper: Tight Bounds for Universal and Cautious Self-stabilizing 1-Maximal Matching.
Proceedings of the Networked Systems - 6th International Conference, 2018

Artificial Neural Network Based Test Escape Screening Using Generative Model.
Proceedings of the IEEE International Test Conference, 2018

Variation-Aware Hardware Trojan Detection through Power Side-channel.
Proceedings of the IEEE International Test Conference, 2018

Evaluating Effects of Hand Pointing by an Image-Based Avatar of a Navigation System.
Proceedings of the Human-Computer Interaction. Interaction in Context, 2018

Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

Decimal Multiplication Using Combination of Software and Hardware.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell.
Integr., 2017

An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan.
IEICE Trans. Inf. Syst., 2017

Byzantine Gathering in Networks with Authenticated Whiteboards.
Proceedings of the WALCOM: Algorithms and Computation, 2017

An Efficient Silent Self-stabilizing 1-Maximal Matching Algorithm Under Distributed Daemon for Arbitrary Networks.
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2017

Brief Announcement: Efficient Self-Stabilizing 1-Maximal Matching Algorithm for Arbitrary Networks.
Proceedings of the ACM Symposium on Principles of Distributed Computing, 2017

Constant-Space Population Protocols for Uniform Bipartition.
Proceedings of the 21st International Conference on Principles of Distributed Systems, 2017

Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
An Efficient Silent Self-Stabilizing 1-Maximal Matching Algorithm in Anonymous Networks.
J. Graph Algorithms Appl., 2016

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair.
IEICE Trans. Inf. Syst., 2016

An Efficient Silent Self-stabilizing 1-Maximal Matching Algorithm Under Distributed Daemon Without Global Identifiers.
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2016

Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
An Efficient Silent Self-Stabilizing Algorithm for 1-Maximal Matching in Anonymous Networks.
Proceedings of the WALCOM: Algorithms and Computation - 9th International Workshop, 2015

An ECC-based memory architecture with online self-repair capabilities for reliability enhancement.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Memory block based scan-BIST architecture for application-dependent FPGA testing.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012
A Failure Prediction Strategy for Transistor Aging.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Test Pattern Ordering and Selection for High Quality Test Set under Constraints.
IEICE Trans. Inf. Syst., 2012

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation.
Proceedings of the 2012 IEEE International Test Conference, 2012

DART: Dependable VLSI test architecture and its implementation.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection.
J. Electron. Test., 2011

Faster-than-at-speed test for increased test quality and in-field reliability.
Proceedings of the 2011 IEEE International Test Conference, 2011

Temperature-Variation-Aware Test Pattern Optimization.
Proceedings of the 16th European Test Symposium, 2011

2010
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Aging test strategy and adaptive test scheduling for SoC failure prediction.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Test pattern selection to optimize delay test quality with a limited size of test set.
Proceedings of the 15th European Test Symposium, 2010

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Seed Ordering and Selection for High Quality Delay Test.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms.
Proceedings of the Distributed Computing, 23rd International Symposium, 2009

Partial Scan Approach for Secret Information Protection.
Proceedings of the 14th IEEE European Test Symposium, 2009

2008
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors.
IEICE Trans. Inf. Syst., 2008

Special Section on Test and Verification of VLSIs.
IEICE Trans. Inf. Syst., 2008

2006
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A Low Power Deterministic Test Using Scan Chain Disable Technique.
IEICE Trans. Inf. Syst., 2006

Design for Testability of Software-Based Self-Test for Processors.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Trans. Inf. Syst., 2005

Delay Fault Testing of Processor Cores in Functional Mode.
IEICE Trans. Inf. Syst., 2005

Instruction-based delay fault self-testing of pipelined processor cores.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Testing Superscalar Processors in Functional Mode.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Instruction-Based Delay Fault Self-Testing of Processor Cores.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Efficient Template Generation for Instruction-Based Self-Test of Processor Cores.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Software-Based Delay Fault Testing of Processor Cores.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Test Synthesis for Datapaths Using Datapath-Controller Functions.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Parallel algorithms for selection on the BSP and BSP* models.
Syst. Comput. Jpn., 2002

A layout adjustment problem for disjoint rectangles preserving orthogonal order.
Syst. Comput. Jpn., 2002

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.
J. Electron. Test., 2002

An Extended Class of Sequential Circuits with Combinational Test Generation Complexity.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
A causal broadcast protocol for distributed mobile systems.
Syst. Comput. Jpn., 2001

Adaptive Long-Lived O(k<sup>2</sup>)-Renaming with O(k<sup>2</sup>) Steps.
Proceedings of the Distributed Computing, 15th International Conference, 2001

2000
Parallelizability of Some P-Complete Problems.
Proceedings of the Parallel and Distributed Processing, 2000

A class of sequential circuits with combinational test generation complexity under single-fault assumption.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
A cost optimal parallel algorithm for weighted distance transforms.
Parallel Comput., 1999

Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

Parallel Selection Algorithms with Analysis on Clusters.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
An approach to test synthesis from higher level.
Integr., 1998

SelfStabilizing WaitFree Clock Synchronization with Bounded Space.
Proceedings of the Distributed Computing, 1998

A High-Level Synthesis Method for Weakly Testable Data Paths.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Non-scan design for testable data paths using thru operation.
Syst. Comput. Jpn., 1997

Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System.
Proceedings of the Distributed Algorithms, 11th International Workshop, 1997

A Parallel Algorithm for Weighted Distance Transforms.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1996
A Snapshot Algorithm for Distributed Mobile Systems.
Proceedings of the 16th International Conference on Distributed Computing Systems, 1996

1994
Linear-Time Snapshot Using Multi-writer Multi-reader Registers.
Proceedings of the Distributed Algorithms, 8th International Workshop, 1994

1992
COM (Cost Oriented Memory) Testing.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992


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