Hideyuki Ichihara

According to our database, Hideyuki Ichihara authored at least 54 papers between 1997 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Resource Estimation Method in Multi-Cloud Environment with a Model Based on a Repairable-Item Inventory System.

Naoki Okuda, Kaori Maeda, Chisa Takano, Hideyuki Ichihara

Proceedings of the 47th IEEE Annual Computers, Software, and Applications Conference, 2023

Reliability Analysis of Approximate Multipliers with Recovery Schemes.

Tamaki Kozuma, Qilin Wang, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application.

Hideyuki Ichihara, Naruki Itoh, Tomoo Inoue

Proceedings of the IEEE International Test Conference in Asia, 2022

2021

A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing.

Hideyuki Ichihara, Takayuki Fukuda, Tomoo Inoue

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

A Design of Approximate Voting Schemes for Fail-Operational Systems.

Hideyuki Ichihara, Kazunori Yukihiro, Tomoo Inoue

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines.

Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019

Compact and Accurate Digital Filters Based on Stochastic Computing.

Hideyuki Ichihara, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue

IEEE Trans. Emerg. Top. Comput., 2019

An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis.

Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the IEEE International Test Conference in Asia, 2019

State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines.

Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2017

State assignment for fault tolerant stochastic computing with linear finite state machines.

Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the International Test Conference in Asia, 2017

2015

Logic simplification by minterm complement for error tolerant application.

Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Designing area-efficient controllers for multi-cycle transient fault tolerant systems.

Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 20th IEEE European Test Symposium, 2015

A practical approach for logic simplification based on fault acceptability for error tolerant application.

Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 20th IEEE European Test Symposium, 2015

A fault tolerant response analyzer with self-error-correction capability.

Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Compact and accurate stochastic circuits with shared random number sources.

Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Scheduling algorithm in datapath synthesis for long duration transient fault tolerance.

Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test.

Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Modeling economics of LSI design and manufacturing for test design selection.

Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool.

Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Hybrid Test Application in Partial Skewed-Load Scan Design.

Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

High-level synthesis for multi-cycle transient fault tolerant datapaths.

Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Test Compression Based on Lossy Image Encoding.

Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Design and Optimization of Transparency-Based TAM for SoC Test.

Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2010

A Practical Threshold Test Generation for Error Tolerant Application.

Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue

IEICE Trans. Inf. Syst., 2010

An FPGA-based fail-soft system with adaptive reconfiguration.

Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Hybrid test application in hybrid delay scan design.

Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 15th European Test Symposium, 2010

A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic.

Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009

Reliability and Performance Analysis of FPGA-Based Fault Tolerant System.

Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A Practical Approach to Threshold Test Generation for Error Tolerant Circuits.

Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A Self-Test of Dynamically Reconfigurable Processors with Test Frames.

Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara

IEICE Trans. Inf. Syst., 2008

An Architecture of Embedded Decompressor with Reconfigurability for Test Compression.

Hideyuki Ichihara, Tomoyuki Saiki, Tomoo Inoue

IEICE Trans. Inf. Syst., 2008

2007

A statistical error model for image sensors and its testing.

Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita

Syst. Comput. Jpn., 2007

A Variable-Length Coding Adjustable for Compressed Test Application.

Hideyuki Ichihara, Toshihiro Ohara, Michihiro Shintani, Tomoo Inoue

IEICE Trans. Inf. Syst., 2007

TAM Design and Optimization for Transparency-Based SoC Test.

Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.

Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara

Proceedings of the 12th European Test Symposium, 2007

Test Compression / Decompression Based on JPEG VLC Algorithm.

Hideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue

Proceedings of the 16th Asian Test Symposium, 2007

2006

A Reconfigurable Embedded Decompressor for Test Compression.

Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

Test cost reduction for logic circuits: Reduction of test data volume and test application time.

Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu

Syst. Comput. Jpn., 2005

Huffman-Based Test Response Coding.

Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue

IEICE Trans. Inf. Syst., 2005

An Effective Design for Hierarchical Test Generation Based on Strong Testability.

Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A Huffman-based coding with efficient test application.

Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Test Decompression Scheme for Variable-Length Coding.

Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG.

Hideyuki Ichihara, Tomoo Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.

Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG.

Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 2003 Design, 2003

Test Response Compression Based on Huffman Coding.

Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding.

Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Dynamic Test Compression Using Statistical Coding.

Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Test Transformation to Improve Compaction by Statistical Encoding.

Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

On Test Generation with A Limited Number of Tests.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.

Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

On invariant implication relations for removing partial circuits.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Syst. Comput. Jpn., 1997

On Acceleration of Logic Circuits Optimization Using Implication Relations.

Hideyuki Ichihara, Kozo Kinoshita

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997