Yul Chu

According to our database1, Yul Chu authored at least 24 papers between 1996 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A flexible multi-core functional cache simulator (FM-SIM).
Proceedings of the Summer Simulation Multi-Conference, 2017

2015
Accuracy Enhanced Distributed Sparse Matrix Solver with Block-Based Pivoting for Large Linear Systems.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

2014
Dual-access way-prediction cache for embedded systems.
EURASIP J. Emb. Sys., 2014

2013
A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches.
IJERTCS, 2013

A Study for a Low-Power Way Predictor for Embedded Data Caches.
Proceedings of the Advanced Technologies, Embedded and Multimedia for Human-centric Computing, 2013

2012
A parallel simulator for network terminal packet buffer.
Simulation, 2012

2009
A Case for a Packet Management in a Network Terminal.
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009

An Efficient Networking Management for a Protocol Processor.
Proceedings of the Third International Conference on the Digital Society (ICDS 2009), 2009

A Dynamic Packet Management in a Protocol Processor.
Proceedings of the Computational Science and Its Applications, 2009

2007
Modeling of Trace- and Block-Based Caches.
Journal of Circuits, Systems, and Computers, 2007

Packet Buffer Management for a High-Speed Network Interface Card.
Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

2006
A low-power cache scheme for embedded computing.
J. Embedded Computing, 2006

A Case for Dual-Mapping One-Way Caches.
Proceedings of the Architecture of Computing Systems, 2006

A Shared-Memory Packet Buffer Management in a Network Interface Card.
Proceedings of the Management of Convergence Networks and Services, 2006

2005
A Study for a Dynamic Branch Target-Prefetching Scheme.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

An Enhanced Dynamic Packet Buffer Management.
Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 2005

Energy savings for data caches: ELRU-SEQ replacement policy.
Proceedings of the 24th IEEE International Performance Computing and Communications Conference, 2005

On Achieving Efficiency and Fairness in Video Transportation.
Proceedings of the Networking, 2005

A Study for Packet Buffer Algorithms for a Protocol Processor.
Proceedings of the Third International Conference on Information Technology and Applications (ICITA 2005), 2005

A Simple Project for Teaching Instruction Set Architecture.
Proceedings of the 5th IEEE International Conference on Advanced Learning Technologies, 2005

A Replacement Policy to Save Energy for Data Cache.
Proceedings of the 19th Annual International Symposium on High Performance Computing Systems and Applications (HPCS 2005), 2005

2001
An Efficient Indirect Branch Predictor.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000
A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1996
Parallel SOLVE for direct circuit simulation on a transputer array.
Proceedings of the 3rd International Conference on High Performance Computing, 1996


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