Yves Joannon

According to our database, Yves Joannon authored at least 4 papers between 2006 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test.

Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro

VLSI Design, 2008

Decreasing Test Qualification Time in AMS and RF Systems.

Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro

IEEE Des. Test Comput., 2008

2007

Qualification of behavioral level design validation for AMS & RF SoCs.

Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro

Proceedings of the IFIP VLSI-SoC 2007, 2007

2006

Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language.

Yves Joannon, Vincent Beroulle, Rami Khouri, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006