Vincent Beroulle

According to our database1, Vincent Beroulle authored at least 59 papers between 2001 and 2018.

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Bibliography

2018
ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods.
J. Hardware and Systems Security, 2018

Security Enhancements of a Mutual Authentication Protocol Used in a HF Full-Fledged RFID Tag.
J. Electronic Testing, 2018

An Evaluation of UHF RFID Anti-Collision Protocols with NS2.
Proceedings of the 9th IFIP International Conference on New Technologies, 2018

Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

On the Importance of Analysing Microarchitecture for Accurate Software Fault Models.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Time Modeling with NS2 in UHF RFID Anti-Collision Protocols.
Proceedings of the 32nd IEEE International Conference on Advanced Information Networking and Applications, 2018

2017
A global approach for the improvement of UHF RFID safety and security.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Enhanced Elliptic Curve Scalar Multiplication Secure Against Side Channel Attacks and Safe Errors.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

2016
ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes.
ACM Trans. Design Autom. Electr. Syst., 2016

Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Clock generator behavioral modeling for supply voltage glitch attack effects analysis.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

On fault injections for early security evaluation vs. laser-based attacks.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Reusing logic masking to facilitate path-delay-based hardware Trojan detection.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

How logic masking can improve path delay analysis for Hardware Trojan detection.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

High output hamming-distance achievement by a greedy logic masking approach.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Implementation of a secured digital ultralight 14443-type A RFID tag with an FPGA platform.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

On the development of a new countermeasure based on a laser attack RTL fault model.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Facilitating side channel analysis by obfuscation for Hardware Trojan detection.
Proceedings of the 10th International Design & Test Symposium, 2015

Validation of RTL laser fault injection model with respect to layout information.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

2014


Fault tolerance evaluation of RFID tags.
Proceedings of the 15th Latin American Test Workshop, 2014

On error models for RTL security evaluations.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Voltage Glitch Attacks on Mixed-Signal Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Emulation based fault injection on UHF RFID transponder.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Assertion based on-line fault detection applied on UHF RFID tag.
Proceedings of the 8th International Design and Test Symposium, 2013

An UHF RFID emulation platform with fault injection and real time monitoring capabilities.
Proceedings of the 8th International Design and Test Symposium, 2013

EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2012
Evaluation of a new RFID system performance monitoring approach.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate.
J. Electronic Testing, 2011

SystemC modeling of RFID systems for robustness analysis.
Proceedings of the 19th International Conference on Software, 2011

Read rate profile monitoring for defect detection in RFID Systems.
Proceedings of the 2011 IEEE International Conference on RFID-Technologies and Applications, 2011

Towards middleware-based fault-tolerance in RFID systems.
Proceedings of the 13th European Workshop on Dependable Computing, 2011

Towards an unified IP verification and robustness analysis platform.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2009
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.
IET Computers & Digital Techniques, 2009

2008
Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test.
VLSI Design, 2008

Decreasing Test Qualification Time in AMS and RF Systems.
IEEE Design & Test of Computers, 2008

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007
Impact of hardware emulation on the verification quality improvement.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Qualification of behavioral level design validation for AMS & RF SoCs.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

VHDL-AMS Modeling of an UWB Radio Link Including Antennas.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Functional Verification of RTL Designs driven by Mutation Testing metrics.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
A DFT Architecture for Asynchronous Networks-on-Chip.
Proceedings of the 11th European Test Symposium, 2006

Design-for-Test of Asynchronous Networks-on-Chip.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

How to Improve a Set of Design Validation Data by Using Mutation-based Test.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Mutation Sampling Technique for the Generation of Structural Test Data.
Proceedings of the 2005 Design, 2005

2004
Design of CMOS MEMS based on mechanical resonators using a RF simulation approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

2002
Reliability analysis of CMOS MEMS structures obtained by Front Side Bulk Micromachining.
Microelectronics Reliability, 2002

Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems.
Proceedings of the 2002 Design, 2002

2001
Test and Testability of a Monolithic MEMS for Magnetic Field Sensing.
J. Electronic Testing, 2001

Impact of Technology Spreading on MEMS design Robustness.
Proceedings of the SOC Design Methodologies, 2001

Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing.
Proceedings of the SOC Design Methodologies, 2001


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