Vincent Beroulle
Orcid: 0000-0003-0617-3087
According to our database1,
Vincent Beroulle
authored at least 101 papers
between 2001 and 2023.
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Bibliography
2023
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
A Study of High Temperature Effects on Ring Oscillator Based Physical Unclonable Functions.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Proceedings of the IEEE European Symposium on Security and Privacy, 2023
Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault Injection.
Proceedings of the Smart Card Research and Advanced Applications, 2023
2022
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms.
ACM Trans. Design Autom. Electr. Syst., 2022
Helper Data Masking for Physically Unclonable Function-Based Key Generation Algorithms.
IEEE Access, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
An Efficient Approach to Model Strong PUF with Multi-Layer Perceptron using Transfer Learning.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine Learning.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained Networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022
2021
Survey: Vulnerability Analysis of Low-Cost ECC-Based RFID Protocols against Wireless and Side-Channel Attacks.
Sensors, 2021
ACM J. Emerg. Technol. Comput. Syst., 2021
IEEE Access, 2021
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Clock skew-based physical authentication protocol for 802.15.4 IR-UWB indoor positioning.
Proceedings of the IoT '20: 10th International Conference on the Internet of Things, 2020
Hardware Security Vulnerability Assessment to Identify the Potential Risks in A Critical Embedded Application.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community.
Proceedings of the IEEE European Test Symposium, 2020
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor.
Microprocess. Microsystems, 2019
Security Evaluation with an Indoor UWB Localization Open Platform: Acknowledgment Attack Case Study.
Proceedings of the 30th IEEE Annual International Symposium on Personal, 2019
Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Analyzing Software Security Against Complex Fault Models with Frama-C Value Analysis.
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019
Fault Injection on Hidden Registers in a RISC-V Rocket Processor and Software Countermeasures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods.
J. Hardw. Syst. Secur., 2018
Security Enhancements of a Mutual Authentication Protocol Used in a HF Full-Fledged RFID Tag.
J. Electron. Test., 2018
Proceedings of the 2018 International Workshop on Secure Internet of Things, 2018
Proceedings of the 9th IFIP International Conference on New Technologies, 2018
Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the 6th International EURASIP Workshop on RFID Technology, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 32nd IEEE International Conference on Advanced Information Networking and Applications, 2018
2017
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
Enhanced Elliptic Curve Scalar Multiplication Secure Against Side Channel Attacks and Safe Errors.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017
2016
ACM Trans. Design Autom. Electr. Syst., 2016
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.
Microprocess. Microsystems, 2016
Clock generator behavioral modeling for supply voltage glitch attack effects analysis.
Microprocess. Microsystems, 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Implementation of a secured digital ultralight 14443-type A RFID tag with an FPGA platform.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the 10th International Design & Test Symposium, 2015
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
An UHF RFID emulation platform with fault injection and real time monitoring capabilities.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
J. Electron. Test., 2011
Proceedings of the 19th International Conference on Software, 2011
Proceedings of the 2011 IEEE International Conference on RFID-Technologies and Applications, 2011
Proceedings of the 13th European Workshop on Dependable Computing, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2009
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.
IET Comput. Digit. Tech., 2009
2008
Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test.
VLSI Design, 2008
IEEE Des. Test Comput., 2008
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Proceedings of the 2005 joint conference on Smart objects and ambient intelligence, 2005
Proceedings of the 2005 Design, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
2002
Reliability analysis of CMOS MEMS structures obtained by Front Side Bulk Micromachining.
Microelectron. Reliab., 2002
Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Testing Resonant Micro-Electro-Mechanical Sensors using the Oscillation-based Test Methodology.
Proceedings of the 3rd Latin American Test Workshop, 2002
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems.
Proceedings of the 2002 Design, 2002
2001
J. Electron. Test., 2001
Impact of Technology Spreading on MEMS design Robustness.
Proceedings of the SOC Design Methodologies, 2001
Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing.
Proceedings of the SOC Design Methodologies, 2001