Zewen Ye

Orcid: 0000-0003-3623-3554

According to our database1, Zewen Ye authored at least 11 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
RVSLH: Acceleration of Postquantum Standard SLH-DSA With Customized RISC-V Processor.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025

PQNTRU: Acceleration of NTRU-Based Schemes via Customized Post-Quantum Processor.
IEEE Trans. Computers, May, 2025

Accelerating Prefilling for Long-Context LLMs via Sparse Pattern Sharing.
CoRR, May, 2025

FastViT: Real-Time Linear Attention Accelerator for Dense Predictions of Vision Transformer (ViT).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

MVQ: Towards Efficient DNN Compression and Acceleration with Masked Vector Quantization.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024
ProgramGalois: A Programmable Generator of Radix-4 Discrete Galois Transformation Architecture for Lattice-Based Cryptography.
ACM Trans. Reconfigurable Technol. Syst., December, 2024

A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

HTCNN: High-Throughput Batch CNN Inference with Homomorphic Encryption for Edge Computing.
IACR Cryptol. ePrint Arch., 2024

MVQ:Towards Efficient DNN Compression and Acceleration with Masked Vector Quantization.
CoRR, 2024

A Folded Computation-in-Memory Accelerator for Fast Polynomial Multiplication in BIKE.
Proceedings of the Euro-Par 2024: Parallel Processing, 2024

2022
PipeNTT: A Pipelined Number Theoretic Transform Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2022


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