Zhen Yang

According to our database, Zhen Yang authored at least 4 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS.

Zhen Yang, Fanyi Meng, Bing Liu, Nengxu Zhu, Zenglong Zhao, Kaixue Ma

IEEE J. Solid State Circuits, October, 2025

Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications.

Zenglong Zhao, Xianghui Chen, Fanyi Meng, Zhen Yang, Bing Liu, Nengxu Zhu, Keping Wang, Kaixue Ma, Kiat Seng Yeo

IEEE J. Solid State Circuits, September, 2025

A 132-to-148GHz CMOS 4TX-4RX FMCW Radar Transceiver Array with Cavity-Backed Antenna-in-Package Achieving 28dBm EIRP.

Bing Liu, Jiancheng Huang, Zhen Yang, Xuguang Li, Jin Zhang, Xu Wang, Hao Shi, Fei Li, Zhenhua Xu, Ruipeng Liu, Shuangxu Li, Yongqiang Wang, Keping Wang, Haipeng Fu, Fanyi Meng, Kaixue Ma

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2023

A 120-GHz Class-F Frequency Doubler With 7.8-dBm P_OUT in 55-nm Bulk CMOS.

Zhen Yang, Kaixue Ma, Fanyi Meng, Bing Liu

IEEE J. Solid State Circuits, 2023