Zheng Wang
Orcid: 0000-0002-3994-0652Affiliations:
- University of Electronic Science and Technology of China, School of Electronic Science and Engineering, Chengdu, China
According to our database1,
Zheng Wang
authored at least 20 papers
between 2019 and 2024.
Collaborative distances:
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Bibliography
2024
A Sub-50-fs<sub>rms</sub> Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm.
IEEE J. Solid State Circuits, March, 2024
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-f<sub>max</sub> Embedded Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
2023
A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving <3.7° RMS Phase Error in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
A novel gain-boosting structure with Z-embedding and parallel pre-embedding network for amplifiers at near-<i>f</i><sub><i>max</i></sub> frequencies.
Int. J. Circuit Theory Appl., October, 2023
Collaborative gain and noise optimization: a design of 150-173-GHz cascode LNA with 22.3 dB gain and 6.92 dB NF based on the gain-noise plane.
Sci. China Inf. Sci., October, 2023
A Study of Collaborative Gain/Noise Optimization for LNAs at Near- Frequencies Based on a Novel Gain-Noise Plane Approach.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
A Compact Frequency Servo SoC with Background Output Power Calibration for Miniaturized Atomic Clocks.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Optimize the Efficiency of Lossy Matching Network: A Top-Down Splitting Algorithm Based on Generalized Quality-Based Equation.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A study on gain boosting techniques of cascode amplifier at near-<i>f</i><sub><i>max</i></sub> frequencies based on gain plane approach.
Microelectron. J., 2021
An Accurate Analytical Model for Small Signal Behavior of MOSFET in Terahertz Applications.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A 150-170GHz 5-Bit Vector-Modulated Phase Shifter Based on X-type Phase Inverter Technique.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A New Method to Extract Mobility Degradation and Parasitic Series Resistance of Nano-scaled MOSFETs.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
An Analytical Model of Energy Band Considering Drain Doping Effect of TFET With Exponential Barrier.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2020
A Novel Design of Double Gain Boosting Inductor Cascode Amplifier at Near-fmax Frequencies.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
Short-channel effects on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs.
Sci. China Inf. Sci., 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
The Design of a 28GHz Mixer-Embedded Frequency Shifting PLL in 65nm CMOS with Low In-Band Phase Noise.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019