Zonglin Ye

According to our database, Zonglin Ye authored at least 12 papers between 2014 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

27.1 A 20GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2fs Jitter and -76.5dBc Worst-Case Fractional Spur.

Zonglin Ye, Yuxuan Sun, Longxiang Hou, Yuhan Ding, Yixuan Wen, Hongyang Zhang, Xinlin Geng, Qian Xie, Shiheng Yang, Zheng Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A 28nm 11.2-to-20-GHz PLL-based 16-Phase Clock Generator with High-Order-Mode Ring Oscillator Achieving 24.3-fs Jitter for 320-Gsps-Sample-Rate Data Converter.

Zonglin Ye, Longxiang Hou, Yuxuan Sun, Yuhan Ding, Yixuan Wen, Hongyang Zhang, Hao Luo, Yi Yang, Chenming Zhang, Xinlin Geng, Qian Xie, Cheng Wang, Jun Zhou, Zheng Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving -80.7dBc Fractional Spur.

Zonglin Ye, Hongyang Zhang, Yuxuan Sun, Xinlin Geng, Qian Xie, Shiheng Yang, Zheng Wang

IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

2024

A Sub-50-fs_rms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm.

Zonglin Ye, Xinlin Geng, Yao Xiao, Qian Xie, Zheng Wang

IEEE J. Solid State Circuits, March, 2024

A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$.

Zonglin Ye, Xinlin Geng, Zhixiang Shi, Hongyang Zhang, Qian Xie, Zheng Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

A Compact Frequency Servo SoC with Background Output Power Calibration for Miniaturized Atomic Clocks.

Xinlin Geng, Zonglin Ye, Kailei Wang, Hongyang Zhang, Qian Xie, Zheng Wang

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels.

Xinlin Geng, Zonglin Ye, Yao Xiao, Qian Xie, Zheng Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance.

Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019

An outlier detection scheme for dynamical sequential datasets.

Shiliang Zhang, Hui Cao, Zonglin Ye, Yanbin Zhang, Xiali Hei

Commun. Stat. Simul. Comput., 2019

A Gas Analysis Model with Uninformative Variable Elimination Using Nonlinearity Compensation by RBFNN.

Panpan Zhang, Yanbin Zhang, Hui Cao, Zonglin Ye, Dapeng Yan, Shuangsi Xue

Proceedings of the 4th IEEE International Conference on Advanced Robotics and Mechatronics, 2019

2016

Outlier factor based partitional clustering analysis with constraints discovery and representative objects generation.

Zonglin Ye, Hui Cao, Yanbin Zhang, Lixin Jia

Neurocomputing, 2016

2014

A suspect point recheck method of fuzzy clustering for robot self-position estimation.

Zonglin Ye, Hui Cao, Yanbin Zhang, Lixin Jia, Gangquan Si

Proceedings of the 13th International Conference on Control Automation Robotics & Vision, 2014