Xinlin Geng
Orcid: 0000-0002-8538-348X
According to our database1,
Xinlin Geng
authored at least 7 papers
between 2019 and 2024.
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Bibliography
2024
A Sub-50-fs<sub>rms</sub> Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm.
IEEE J. Solid State Circuits, March, 2024
2023
A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving <3.7° RMS Phase Error in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
A Compact Frequency Servo SoC with Background Output Power Calibration for Miniaturized Atomic Clocks.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2019
The Design of a 28GHz Mixer-Embedded Frequency Shifting PLL in 65nm CMOS with Low In-Band Phase Noise.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019