Zhengwang Cheng

Orcid: 0000-0001-7013-7190

According to our database¹, Zhengwang Cheng authored at least 9 papers between 2022 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Links

On csauthors.net:

Bibliography

2026

A wideband low-phase-noise VCO with low-coupled 8-shaped inductor.

[BibT_eX]

[DOI]

Microelectron. J., 2026

2025

A 17.8-20.6 GHz Low Phase Noise VCO with Low-Coupled 8-Shaped Transformer.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., October, 2025

Design and analysis of a ring-VCO based low jitter PLL.

[BibT_eX]

[DOI]

Microelectron. J., 2025

A Synchronous Buck Converter With a Wide Input Voltage Range Using Simulated Peak Current Mode Control.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2025

A Four-Core Dual-Mode VCO With a Frequency Range of 19.92-40.17 GHz Using Current Reuse and Transconductance Unit Switching Techniques.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2025

An Efficient 2.4 GHz Polar Class-G Switched-Capacitor Power Amplifier With a Five-Transistors Voltage-Tolerant Switch.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2025

2023

A 3.83-5.55 GHz high frequency resolution DCO with optimized switched-capacitor ladder and low-coupled eight-shaped transformer.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., December, 2023

Design and analysis of a low phase noise low power ring-VCO.

[BibT_eX]

[DOI]

IEICE Electron. Express, December, 2023

2022

A 45MHz-2.5GHz broadband CMOS up-conversion mixer with a bisymmetric class-AB input stage.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

Zhengwang Cheng

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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