Zhenyuan Liu

Orcid: 0009-0001-2334-6130

Affiliations:

Worcester Polytechnic Institute, Worcester, USA

According to our database¹, Zhenyuan Liu authored at least 8 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2025

GlitchGlück: Enabling Software Vulnerabilities through Guided Hardware Fault Injection.

[BibT_eX]

[DOI]

Zhenyuan Liu

Dillibabu Shanmugam

Patrick Schaumont

Proceedings of the 19th USENIX WOOT Conference on Offensive Technologies, 2025

Telescope: Top-Down Hierarchical Pre-silicon Side-channel Leakage Assessment in System-on-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Asia Conference on Computer and Communications Security, 2025

μScan: Deep Learning Detection of Faulty Micro-architecture States and Patterns from Scan-Chain Data.

[BibT_eX]

[DOI]

Proceedings of the Applied Cryptography and Network Security Workshops, 2025

2024

Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis.

[BibT_eX]

[DOI]

Jasper Van Woudenberg

IEEE Trans. Emerg. Top. Comput., 2024

FaultDetective Explainable to a Fault, from the Design Layout to the Software.

[BibT_eX]

[DOI]

Zhenyuan Liu

Dillibabu Shanmugam

Patrick Schaumont

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2022

Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis.

[BibT_eX]

[DOI]

Jasper Van Woudenberg

CoRR, 2022

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment.

[BibT_eX]

[DOI]

Pantea Kiaei

Zhenyuan Liu

Patrick Schaumont

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

Saidoyoki: Evaluating side-channel leakage in pre- and post-silicon setting.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

Zhenyuan Liu

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Bibliography

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