Patrick Schaumont

According to our database1, Patrick Schaumont authored at least 196 papers between 1995 and 2019.

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Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

A Secure Exception Mode for Fault-Attack-Resistant Processing.
IEEE Trans. Dependable Sec. Comput., 2019

SKIVA: Flexible and Modular Side-channel and Fault Countermeasures.
IACR Cryptology ePrint Archive, 2019

SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

Secure Intermittent Computing Protocol: Protecting State Across Power Loss.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Special Section on Secure Computer Architectures.
IEEE Trans. Computers, 2018

Fault Attacks on Secure Embedded Software: Threats, Design, and Evaluation.
J. Hardware and Systems Security, 2018

Identifying and Eliminating Side-Channel Leaks in Programmable Systems.
IEEE Design & Test, 2018

The Rise of Hardware Security in Computer Architectures.
IEEE Computer, 2018

Exploiting Security Vulnerabilities in Intermittent Computing.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018

Eliminating timing side-channel leaks using program repair.
Proceedings of the 27th ACM SIGSOFT International Symposium on Software Testing and Analysis, 2018

Fault-assisted side-channel analysis of masked implementations.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Secure Application Continuity in Intermittent Systems.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Inducing local timing fault through EM injection.
Proceedings of the 55th Annual Design Automation Conference, 2018

A Low-cost Function Call Protection Mechanism Against Instruction Skip Fault Attacks.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018

2017
Analyzing the Fault Injection Sensitivity of Secure Embedded Software.
ACM Trans. Embedded Comput. Syst., 2017

Vector Instruction Set Extensions for Efficient Computation of Keccak.
IEEE Trans. Computers, 2017

Security by compilation: an automated approach to comprehensive side-channel resistance.
SIGLOG News, 2017

Stateless leakage resiliency from NLFSRs.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

A new maskless debiasing method for lightweight physical unclonable functions.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Security in the Internet of Things: A challenge of scale.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimizing Cryptography in Energy Harvesting Applications.
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017

Employing dual-complementary flip-flops to detect EMFI attacks.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Precomputation Methods for Hash-Based Signatures on Energy-Harvesting Platforms.
IEEE Trans. Computers, 2016

Secure authentication with energy-harvesting: A multi-dimensional balancing act.
SUSCOM, 2016

Compact and low-power ASIP design for lightweight PUF-based authentication protocols.
IET Information Security, 2016

Keymill: Side-Channel Resilient Key Generator.
IACR Cryptology ePrint Archive, 2016

Analyzing the Efficiency of Biased-Fault Based Attacks.
Embedded Systems Letters, 2016

Foundations of Secure Scaling (Dagstuhl Seminar 16342).
Dagstuhl Reports, 2016

Keymill: Side-Channel Resilient Key Generator, A New Concept for SCA-Security by Design - A New Concept for SCA-Security by Design.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016

Lightweight Fault Attack Resistance in Software Using Intra-instruction Redundancy.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016

A Configurable and Lightweight Timing Monitor for Fault Attack Detection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

Software Fault Resistance is Futile: Effective Single-Glitch Attacks.
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016

A design method for remote integrity checking of complex PCBs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Key Updating for Leakage Resiliency With Application to AES Modes of Operation.
IEEE Trans. Information Forensics and Security, 2015

Introduction for Embedded Platforms for Cryptography in the Coming Decade.
ACM Trans. Embedded Comput. Syst., 2015

The Future of Real-Time Security: Latency-Optimized Lattice-Based Digital Signatures.
ACM Trans. Embedded Comput. Syst., 2015

Quantitative Masking Strength: Quantifying the Power Side-Channel Resistance of Software Code.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Hardware/software co-design of physical unclonable function based authentications on FPGAs.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

BitCryptor: Bit-Serialized Compact Crypto Engine on Reconfigurable Hardware.
IACR Cryptology ePrint Archive, 2015

Analyzing the Efficiency of Biased-Fault Based Attacks.
IACR Cryptology ePrint Archive, 2015

Precomputation Methods for Faster and Greener Post-Quantum Cryptography on Emerging Embedded Platforms.
IACR Cryptology ePrint Archive, 2015

BitCryptor: Bit-Serialized Flexible Crypto Engine for Lightweight Applications.
Proceedings of the Progress in Cryptology - INDOCRYPT 2015, 2015

TVVF: Estimating the vulnerability of hardware cryptosystems against timing violation attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Improving Fault Attacks on Embedded Software Using RISC Pipeline Characterization.
Proceedings of the 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2015

Differential Fault Intensity Analysis on PRESENT and LED Block Ciphers.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2015

End-To-End Design of a PUF-Based Privacy Preserving Authentication Protocol.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

2014
The Impact of Aging on a Physical Unclonable Function.
IEEE Trans. VLSI Syst., 2014

Formal Verification of Software Countermeasures against Side-Channel Attacks.
ACM Trans. Softw. Eng. Methodol., 2014

Design Methods for Secure Hardware (NII Shonan Meeting 2014-11).
NII Shonan Meet. Rep., 2014

SIMON Says, Break the Area Records for Symmetric Key Block Ciphers on FPGAs.
IACR Cryptology ePrint Archive, 2014

SIMON Says: Break Area Records of Block Ciphers on FPGAs.
Embedded Systems Letters, 2014

Application design and performance evaluation for multiprocessor sensor nodes.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

SMT-Based Verification of Software Countermeasures against Side-Channel Attacks.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2014

Energy Budget Analysis for Signature Protocols on a Self-powered Wireless Sensor Node.
Proceedings of the Radio Frequency Identification: Security and Privacy Issues, 2014

A Flexible and Compact Hardware Architecture for the SIMON Block Cipher.
Proceedings of the Lightweight Cryptography for Security and Privacy, 2014

Side-channel countermeasure for SHA-3 at almost-zero area overhead.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Hardware-software co-design for heterogeneous multiprocessor sensor nodes.
Proceedings of the IEEE Global Communications Conference, 2014

Differential Fault Intensity Analysis.
Proceedings of the 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2014

Innovative engineering outreach using Intel® security and embedded tools.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Analyzing and eliminating the causes of fault sensitivity analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

QMS: Evaluating the Side-Channel Resistance of Masked Software from Source Code.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks.
IEEE Trans. Computers, 2013

Design and benchmarking of an ASIC with five SHA-3 finalist candidates.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Introduction to the CHES 2012 special issue.
J. Cryptographic Engineering, 2013

Three Design Dimensions of Secure Embedded Systems.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2013

Energy-Architecture Tuning for ECC-Based RFID Tags.
Proceedings of the Radio Frequency Identification, 2013

PASC: Physically authenticated stable-clocked soc platform on low-cost FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

The exponential impact of creativity in computer engineering education.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Differential Power Analysis of MAC-Keccak at Any Key-Length.
Proceedings of the Advances in Information and Computer Security, 2013

SIMD acceleration of modular arithmetic on contemporary embedded platforms.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

Side-Channel Analysis of MAC-Keccak.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Low-cost and area-efficient FPGA implementations of lattice-based cryptography.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Study of ASIC technology impact factors on performance evaluation of SHA-3 candidates.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Digital fingerprints for low-cost platforms using MEMS sensors.
Proceedings of the Workshop on Embedded Systems Security, 2013

2012
A Robust Physical Unclonable Function With Enhanced Challenge-Response Set.
IEEE Trans. Information Forensics and Security, 2012

A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication.
Int. J. Reconfig. Comp., 2012

Simulating power/energy consumption of sensor nodes with flexible hardware in wireless networks.
Proceedings of the 9th Annual IEEE Communications Society Conference on Sensor, 2012

A novel profiled side-channel attack in presence of high Algorithmic Noise.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A novel microprocessor-intrinsic Physical Unclonable Function.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

ASIC implementations of five SHA-3 finalists.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A Parallel Implementation of Montgomery Multiplication on Multicore Systems: Algorithm, Analysis, and Prototype.
IEEE Trans. Computers, 2011

Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive.
J. Cryptology, 2011

A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions.
IACR Cryptology ePrint Archive, 2011

SUNSHINE extension: a hardware-software emulator for flexible sensor nodes in wireless networks.
Proceedings of the 9th International Conference on Embedded Networked Sensor Systems, 2011

A software-hardware emulator for sensor networks.
Proceedings of the 8th Annual IEEE Communications Society Conference on Sensor, 2011

System integration of Elliptic Curve Cryptography on an OMAP platform.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic Units.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A Simulator for Flexible Sensor Nodes in Wireless Networks.
Proceedings of the Seventh International Conference on Mobile Ad-hoc and Sensor Networks, 2011

The Impact of Aging on an FPGA-Based Physical Unclonable Function.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Pre-silicon Characterization of NIST SHA-3 Final Round Candidates.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
From Statistics to Circuits: Foundations for Future Physical Unclonable Functions.
Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010

Optimized System-on-Chip Integration of a Programmable ECC Coprocessor.
TRETS, 2010

A Flexible Design Flow for Software IP Binding in FPGA.
IEEE Trans. Industrial Informatics, 2010

Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

SUNSHINE: a multi-domain sensor network simulator.
Mobile Computing and Communications Review, 2010

On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings.
IACR Cryptology ePrint Archive, 2010

Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore.
IACR Cryptology ePrint Archive, 2010

A Large Scale Characterization of RO-PUF.
Proceedings of the HOST 2010, 2010

State-of-the-art of Secure ECC Implementations: A Survey on Known Side-channel Attacks and Countermeasures.
Proceedings of the HOST 2010, 2010

pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2010

A comprehensive analysis of performance and side-channel-leakage of AES SBOX implementations in embedded software.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Implementing virtual secure circuit using a custom-instruction approach.
Proceedings of the 2010 International Conference on Compilers, 2010

An Analysis of Delay Based PUF Implementations on FPGA.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Demonstrating end point security in embedded systems.
Proceedings of the Secure Integrated Circuits and Systems, 2010

A Practical Introduction to Hardware/Software Codesign.
Springer, ISBN: 978-1-4419-5999-7, 2010

2009
Guest Editors' Introduction to Security in Reconfigurable Systems Design.
TRETS, 2009

A Comparative Analysis of Delay Based PUF Implementations on FPGA.
IACR Cryptology ePrint Archive, 2009

A flexible design flow for software IP binding in commodity FPGA.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.
Proceedings of the Advances in Information Security and Assurance, 2009

Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Extended Abstract: Early Feedback on Side-Channel Risks with Accelerated Toggle-Counting.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Physical unclonable function and true random number generator: a compact and scalable implementation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Impact and compensation of correlated process variation on ring oscillator based puf.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage.
Proceedings of the Design, Automation and Test in Europe, 2009

Engineering On-Chip Thermal Effects.
Proceedings of the Foundations for Forgery-Resilient Cryptographic Hardware, 05.07., 2009

Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
A Hardware Interface for Hashing Algorithms.
IACR Cryptology ePrint Archive, 2008

Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Intellectual Property Protection for Embedded Sensor Nodes.
Proceedings of the Embedded Computer Systems: Architectures, 2008

MEMOCODE 2008 Co-Design Contest.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Slicing Up a Perfect Hardware Masking Scheme.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

2007
Guest Editors' Introduction: Security and Trust in Embedded-Systems Design.
IEEE Design & Test of Computers, 2007

A Senior-Level Course in Hardware-Software Codesign.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

VT Matrix Multiply Design for MEMOCODE '07.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Design methods for security and trust.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Secure FPGA circuits using controlled placement and routing.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Masking and Dual-Rail Logic Don't Add Up.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

2006
An interactive codesign environment for domain-specific coprocessors.
ACM Trans. Design Autom. Electr. Syst., 2006

Multilevel Design Validation in a Secure Embedded System.
IEEE Trans. Computers, 2006

Securing Embedded Systems.
IEEE Security & Privacy, 2006

A Component-Based Design Environment for ESL Design.
IEEE Design & Test of Computers, 2006

Changing the Odds Against Masked Logic.
Proceedings of the Selected Areas in Cryptography, 13th International Workshop, 2006

Side-Channel Leakage Tolerant Architectures.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Executing Hardware as Parallel Software for Picoblaze Networks.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Process Isolation for Reconfigurable Hardware.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Design with race-free hardware semantics.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Offline Hardware/Software Authentication for Reconfigurable Platforms.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Skiing the embedded systems mountain.
ACM Trans. Embedded Comput. Syst., 2005

Platform-based design for an embedded-fingerprint-authentication device.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Integrated modelling and generation of a reconfigurable network-on-chip.
IJES, 2005

Extended abstract: a race-free hardware modeling language.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Multilevel design validation in a secure embedded system.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip.
Proceedings of the 2005 Design, 2005

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
Proceedings of the 42nd Design Automation Conference, 2005

Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design.
Proceedings of the 42nd Design Automation Conference, 2005

Microcoded coprocessor for embedded secure biometric authentication systems.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004
Architectural Design Features of a Programmable High Throughput AES Coprocessor.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Embedded Software Integration for Coarse-Grain Reconfigurable Systems.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Integrated Modeling and Generation of a Reconfigurable Network-on-Chip.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.
Proceedings of the 2004 Design, 2004

Interactive Cosimulation with Partial Evaluation.
Proceedings of the 2004 Design, 2004

The happy marriage of architecture and application in next-generation reconfigurable systems.
Proceedings of the First Conference on Computing Frontiers, 2004

Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Domain-Specific Codesign for Embedded Security.
IEEE Computer, 2003

Teaching Trade-offs in System-level Design Methodologies.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Testing ThumbPod: Softcore bugs are hard to find.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system.
Proceedings of the 40th Design Automation Conference, 2003

Finding the best system design flow for a high-speed JPEG encoder.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
The Journal of Supercomputing, 2002

Domain Specific Tools and Methods for Application in Security Processor Design.
Design Autom. for Emb. Sys., 2002

Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Techniques to Evolve a C++ Based System Design Language.
Proceedings of the 2002 Design, 2002

Unlocking the design secrets of a 2.29 Gb/s Rijndael processor.
Proceedings of the 39th Design Automation Conference, 2002

A Security Protocol for Biometric Smart Cards.
Proceedings of the Fifth Smart Card Research and Advanced Application Conference, 2002

2001
Interoperability as a design issue in C++ based modeling environments.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2001

A SW/HW Interface API for Java/FPGA Co-Designed Applets.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

A Quick Safari Through the Reconfiguration Jungle.
Proceedings of the 38th Design Automation Conference, 2001

Panel: The Next HDL: If C++ is the Answer, What was the Question?
Proceedings of the 38th Design Automation Conference, 2001

Hardware/software partitioning of embedded system in OCAPI-xl.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Virtual Java/FPGA interface for networked reconfiguration.
Proceedings of ASP-DAC 2001, 2001

2000
A Hardware Virtual Machine for the Networked Reconfiguration.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Functional verification of an embedded network component by co-simulation with a real network.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Standards for System-Level Design: Practical Reality or Solution in Search of a Question?
Proceedings of the 2000 Design, 2000

1999
A new algorithm for elimination of common subexpressions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement.
Proceedings of the 1999 Design, 1999

Hardware Reuse at the Behavioral Level.
Proceedings of the 36th Conference on Design Automation, 1999

A 10 Mbit/s Upstream Cable Modem with Automatic equalization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Low Power Digital Frequency Conversion Architectures.
VLSI Signal Processing, 1998

A Technique for Combined Virtual Prototyping and Hardware Design.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A Programming Environment for the Design of Complex High Speed ASICs.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination.
Proceedings of the 10th International Symposium on System Synthesis, 1997

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications.
Proceedings of the European Design and Test Conference, 1997

1995
Synthesis of pipelined DSP accelerators with dynamic scheduling.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995


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