Zhiheng Wang
Orcid: 0000-0003-4080-7418Affiliations:
- University of Minnesota Twin Cities, Department of Electrical and Computer Engineering, Minneapolis, MN, USA
According to our database1,
Zhiheng Wang
authored at least 8 papers
between 2015 and 2020.
Collaborative distances:
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Bibliography
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
ACM Trans. Reconfigurable Technol. Syst., 2020
2019
A 0.4-1.0 GHz, 47 MHop/s Frequency-Hopped TXR Front End With 20 dB In-Band Blocker Rejection.
IEEE J. Solid State Circuits, 2019
2018
Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map.
IEEE Trans. Very Large Scale Integr. Syst., 2017
2015
Randomness meets feedback: stochastic implementation of logistic map dynamical system.
Proceedings of the 52nd Annual Design Automation Conference, 2015